diff mbox

[i386] : "mov $0, reg" and "mov $-1", reg peepholes cleanup

Message ID CAFULd4Z98ZzV9CGxnZQOU+tRz+egbPN+Fov3H5ES09Ht_HFf4Q@mail.gmail.com
State New
Headers show

Commit Message

Uros Bizjak April 28, 2016, 4:32 p.m. UTC 
No functional changes.

2016-04-28  Uros Bizjak  <ubizjak@gmail.com>

    * config/i386/i386.md (zeroing peephole2): Use general_reg_operand.
    (or $-1,reg peephole2): Ditto.
    (strict_low_part zeroing peephole2): Use SWI12 mode iterator.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Committed to mainline SVN.

Uros.
diff mbox

Patch

Index: i386.md
===================================================================
--- i386.md	(revision 235561)
+++ i386.md	(working copy)
@@ -18120,13 +18120,12 @@ 
 				copy_rtx (operands[2]));
 })
 
-;; Attempt to always use XOR for zeroing registers.
+;; Attempt to always use XOR for zeroing registers (including FP modes).
 (define_peephole2
-  [(set (match_operand 0 "register_operand")
+  [(set (match_operand 0 "general_reg_operand")
 	(match_operand 1 "const0_operand"))]
   "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
    && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
-   && GENERAL_REGNO_P (REGNO (operands[0]))
    && peep2_regno_dead_p (0, FLAGS_REG)"
   [(parallel [(set (match_dup 0) (const_int 0))
 	      (clobber (reg:CC FLAGS_REG))])]
@@ -18133,11 +18132,9 @@ 
   "operands[0] = gen_lowpart (word_mode, operands[0]);")
 
 (define_peephole2
-  [(set (strict_low_part (match_operand 0 "register_operand"))
+  [(set (strict_low_part (match_operand:SWI12 0 "general_reg_operand"))
 	(const_int 0))]
-  "(GET_MODE (operands[0]) == QImode
-    || GET_MODE (operands[0]) == HImode)
-   && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
+  "(! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
    && peep2_regno_dead_p (0, FLAGS_REG)"
   [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
 	      (clobber (reg:CC FLAGS_REG))])])
@@ -18144,10 +18141,9 @@ 
 
 ;; For HI, SI and DI modes, or $-1,reg is smaller than mov $-1,reg.
 (define_peephole2
-  [(set (match_operand:SWI248 0 "register_operand")
+  [(set (match_operand:SWI248 0 "general_reg_operand")
 	(const_int -1))]
-  "(optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR)
-   && GENERAL_REGNO_P (REGNO (operands[0]))
+  "(TARGET_MOVE_M1_VIA_OR || optimize_insn_for_size_p ())
    && peep2_regno_dead_p (0, FLAGS_REG)"
   [(parallel [(set (match_dup 0) (const_int -1))
 	      (clobber (reg:CC FLAGS_REG))])]