From patchwork Wed Apr 5 07:42:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 747108 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vyd9K0wVSz9s7n for ; Wed, 5 Apr 2017 17:42:44 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="lYb/FF19"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; q=dns; s=default; b=KGVpuFjaaXCRQQf L+ytwDH+SHMVZjepKp15B/x7zBrXweGq8dvQT9jsHYMA7STwWJqI2FV+GAqByYmb hzxEJKYq3lIWiHKnxZVpdDykTSKvrXIn+oi3bbD7gXIhDRE5t8oTsA6aBM+s3i16 SUkdN4+RPp8XKtkJ/yOS0C32lROI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:from:date:message-id :subject:to:cc:content-type; s=default; bh=6d7slFsknKRLT6gd5g26t SzSXs4=; b=lYb/FF19yyyxlWMButvAE106wDdonfRLYpMFPpA+KlaiE2yGekOjh ZHic44B07lHW+OsAyyzkkG0bOgT+GsrebBDa1TIGZNMC0iyS9HZCIIsorzKiuCCo xbYVELLMdYSbwuzkty/wAjGC4kWv73RdRRYf3AkSFDBgZe4KoA6Ci4= Received: (qmail 123750 invoked by alias); 5 Apr 2017 07:42:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 123734 invoked by uid 89); 5 Apr 2017 07:42:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.0 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-ua0-f175.google.com Received: from mail-ua0-f175.google.com (HELO mail-ua0-f175.google.com) (209.85.217.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 05 Apr 2017 07:42:32 +0000 Received: by mail-ua0-f175.google.com with SMTP id d64so3063409uad.2 for ; Wed, 05 Apr 2017 00:42:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=1C9m4PYAoI+2O+7ApKGqLy5yL9wBoB3pC1ZBEJH3fBQ=; b=MfQ3bu3TyzA3qfqEYR3sF0h2H8Y+XNbsvj7cRrgap5HIEhvBKGVM6BOlGY/cWZDzbJ nho9q0Rgv2OY05xN8WYTueiLYfUrB80cP4QUshbrk0+uAbTp/XQzyho2SSPHY1kV6fSg TXxeLDlRWPWtkNKeekp9uM6+Nemj4Z1ujP/C6/D+iuzHCWbPEQlVDxI32e49c6ltVw1n B5obZVq8MD57kEjLlyJxCZb8r5L4LPM6fI7ncf20kVPgyZCo2AR+Irr6ES2KA1Ao5bmu zvmLF2Eue2DiR5ZQs6LmDdZUxzok0x1C+dbhby7260dFfOzcUBpn3pjWe41sVCHjHBFa 0jRA== X-Gm-Message-State: AFeK/H1FCj3TkUbuJHaYrPYoA5Q0DM+O4PDxgLatfIHjgaPDLzBIjxMiaI/ODgzM9J4YAPKySWDDwKot5vfn/w== X-Received: by 10.176.75.148 with SMTP id v20mr13129844uaf.165.1491378151837; Wed, 05 Apr 2017 00:42:31 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.183.3 with HTTP; Wed, 5 Apr 2017 00:42:31 -0700 (PDT) In-Reply-To: <20170404192447.GL17461@tucnak> References: <20170404192447.GL17461@tucnak> From: Uros Bizjak Date: Wed, 5 Apr 2017 09:42:31 +0200 Message-ID: Subject: Re: [PATCH] Don't error about x86 return value in SSE reg (or x86 reg) or argument in SSE reg too early (PR target/80298) To: Jakub Jelinek Cc: "gcc-patches@gcc.gnu.org" On Tue, Apr 4, 2017 at 9:24 PM, Jakub Jelinek wrote: > Hi! > > aggregate_value_p is called often very early during compilation, e.g. > from allocate_function or during gimplification of a call with lhs. > The problem with that is e.g. that on x86_64 -m64 -mno-sse we can't > include , because the always_inline inline functions > in mmx and 3dnow intrinsic headers return __m64 or take __m64 as arguments > and that in the 64-bit ABI is in SSE register. > > The following patch makes sure we diagnose this only later (e.g. when > expanding a function to RTL or when expanding calls to other functions), > which means we don't diagnose e.g. inline functions that got successfully > inlined (because then there is really no function return in SSE or x87 > reg) or e.g. for builtin calls if they are emitted inline rather than > as a library call (again, I think that is desirable). > I had to tweak a few tests because the reported line changed slightly, > and in the last test add -fno-builtin-fminl, because otherwise fminl > is expanded inline and again there is no call left with the problem. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? No, I think the issue should be fixed in intrinsics. Attached patch solves this problem for me, and also fixes a couple of similar problems (one with -m3dnowa, that is nowadays a regular compile option). The patched intrinsics were tested with combinations of -m{,no-}sse{,2}, -m{,no-}mmx, -m{-no}3dnow{,a}, -m64, and there were no problems with any combination. Uros. diff --git a/gcc/config/i386/mm3dnow.h b/gcc/config/i386/mm3dnow.h index c8a91a1..2d5c538 100644 --- a/gcc/config/i386/mm3dnow.h +++ b/gcc/config/i386/mm3dnow.h @@ -30,9 +30,13 @@ #include #include -#ifndef __3dNOW__ +#if defined __x86_64__ && !defined __SSE__ || !defined __3dNOW__ #pragma GCC push_options +#ifdef __x86_64__ +#pragma GCC target("sse,3dnow") +#else #pragma GCC target("3dnow") +#endif #define __DISABLE_3dNOW__ #endif /* __3dNOW__ */ @@ -176,7 +180,20 @@ _m_to_float (__m64 __A) return __tmp.a[0]; } -#ifdef __3dNOW_A__ +#ifdef __DISABLE_3dNOW__ +#undef __DISABLE_3dNOW__ +#pragma GCC pop_options +#endif /* __DISABLE_3dNOW__ */ + +#if defined __x86_64__ && !defined __SSE__ || !defined __3dNOW_A__ +#pragma GCC push_options +#ifdef __x86_64__ +#pragma GCC target("sse,3dnowa") +#else +#pragma GCC target("3dnowa") +#endif +#define __DISABLE_3dNOW_A__ +#endif /* __3dNOW_A__ */ extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _m_pf2iw (__m64 __A) @@ -208,11 +225,9 @@ _m_pswapd (__m64 __A) return (__m64)__builtin_ia32_pswapdsf ((__v2sf)__A); } -#endif /* __3dNOW_A__ */ - -#ifdef __DISABLE_3dNOW__ -#undef __DISABLE_3dNOW__ +#ifdef __DISABLE_3dNOW_A__ +#undef __DISABLE_3dNOW_A__ #pragma GCC pop_options -#endif /* __DISABLE_3dNOW__ */ +#endif /* __DISABLE_3dNOW_A__ */ #endif /* _MM3DNOW_H_INCLUDED */ diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h index 957d766..2cb73e3 100644 --- a/gcc/config/i386/mmintrin.h +++ b/gcc/config/i386/mmintrin.h @@ -27,9 +27,13 @@ #ifndef _MMINTRIN_H_INCLUDED #define _MMINTRIN_H_INCLUDED -#ifndef __MMX__ +#if defined __x86_64__ && !defined __SSE__ || !defined __MMX__ #pragma GCC push_options +#ifdef __x86_64__ +#pragma GCC target("sse,mmx") +#else #pragma GCC target("mmx") +#endif #define __DISABLE_MMX__ #endif /* __MMX__ */ @@ -311,7 +315,7 @@ _m_paddd (__m64 __m1, __m64 __m2) /* Add the 64-bit values in M1 to the 64-bit values in M2. */ #ifndef __SSE2__ #pragma GCC push_options -#pragma GCC target("sse2") +#pragma GCC target("sse2,mmx") #define __DISABLE_SSE2__ #endif /* __SSE2__ */ @@ -423,7 +427,7 @@ _m_psubd (__m64 __m1, __m64 __m2) /* Add the 64-bit values in M1 to the 64-bit values in M2. */ #ifndef __SSE2__ #pragma GCC push_options -#pragma GCC target("sse2") +#pragma GCC target("sse2,mmx") #define __DISABLE_SSE2__ #endif /* __SSE2__ */