From patchwork Tue Dec 27 14:13:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 708977 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tnyWv67tNz9t2D for ; Wed, 28 Dec 2016 01:13:31 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="TH/RLF5x"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=FnA6gNIhY0E2c3fFt0UzLxGSQ3xVDDnGxgGjyG7GrWp7iE 55ARqVZW9Du98d58aM4y8nsrwaaVzCSJb0hoADFdrPp6VGBJw25laBeD/Qolj9UU 8csR5H3dQM72KumhrULyZqfT1ah446F0fK1UzUvM5vlxdnv5/OgMBEM61dGvY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=kvyxOc1a4UvW3bPsMnXyBRnMEnY=; b=TH/RLF5xBah1xGD4Gazr 4ABODeWf/ZhokfMeAy5TXUf6lWs0C7venCaiADLvw34pAfxejjE25z8hcmr718c/ Vx3oYWccdyt2w07K3+/la+dfN5gCOt23u1hYAwP/5ENsQDw0FbxnNeG2S4H4eTeG BxEDzw83uqpFWVrCwpnOi4o= Received: (qmail 33655 invoked by alias); 27 Dec 2016 14:13:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 33601 invoked by uid 89); 27 Dec 2016 14:13:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.3 required=5.0 tests=AWL, BAYES_50, FREEMAIL_FROM, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=no version=3.3.2 spammy=QQ, qm, ubizjak@gmail.com, ubizjakgmailcom X-HELO: mail-ua0-f182.google.com Received: from mail-ua0-f182.google.com (HELO mail-ua0-f182.google.com) (209.85.217.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 27 Dec 2016 14:13:11 +0000 Received: by mail-ua0-f182.google.com with SMTP id v2so8837042uac.2 for ; Tue, 27 Dec 2016 06:13:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=qmiSuoJ7tTyrbTZ4u2NBA6Sb9jv+pl7z4zONyo6j8kw=; b=sv0g10vlJ5tEyUT0glyVwpmX1wL7TcF7BCvnNFwiDhZv/LFq4eGdDda1x8fYT49JeP TFJw1H9q9DLxNXsrVAewpjNZem4Ames4Ge2pZpbvnr1ntCXfDCZYVwXZTITmC8TcbGI3 NgOWcJphoPU2hCc49xXxbYMWMFhMzpa64fDlzu2f7gxsUWQH8y0oyfiy3TE0LDZee/CZ tiTpPxPnidzDXQPqZHCYckHXFJDSkHTugr0BsGPerPU7I477yx+VZYJ+UdqLBJ01Zdtm 5Gxx2tCP4wSo7urXMtps6YtxoTx/yloT4j1M3I+WTfYpLdQT64tyzi24lfDEVhIzAQul 8MSg== X-Gm-Message-State: AIkVDXLPtpwXDj+oT+7ZJ52M82VPgMYRyM3wRbvfgZZObq37eMt6hZyNcl/7z9l/Gnk9cGoMqVIBNw1DvZRcgg== X-Received: by 10.159.35.118 with SMTP id 109mr25256544uae.113.1482847989640; Tue, 27 Dec 2016 06:13:09 -0800 (PST) MIME-Version: 1.0 Received: by 10.103.87.11 with HTTP; Tue, 27 Dec 2016 06:13:09 -0800 (PST) From: Uros Bizjak Date: Tue, 27 Dec 2016 15:13:09 +0100 Message-ID: Subject: [PATCH, i386]: Allow constant memory for x86_64 operations involving high registers To: "gcc-patches@gcc.gnu.org" Hello! While we can't allow only non-REX memory operands in patterns involving high registers, we can at least allow constant memory operands here. 2016-12-27 Uros Bizjak PR target/78904 * config/i386/constraints.md (Bc): New special memory constraint. * config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use Bc constraint with nonimmediate_operand to allow constant memory operands. (*cmpqi_ext_3, insv_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1) (*qi_ext_1, *xorqi_ext_1_cc): Use Bc constraint with general_operand to allow constant memory operands. testsuite/ChangeLog: 2016-12-27 Uros Bizjak PR target/78904 * gcc.target/i386/pr78904-3.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/constraints.md =================================================================== --- config/i386/constraints.md (revision 243932) +++ config/i386/constraints.md (working copy) @@ -168,6 +168,7 @@ ;; f FLAGS_REG ;; g GOT memory operand. ;; m Vector memory operand +;; c Constant memory operand ;; s Sibcall memory operand, not valid for TARGET_X32 ;; w Call memory operand, not valid for TARGET_X32 ;; z Constant call address operand. @@ -185,6 +186,11 @@ "@internal Vector memory operand." (match_operand 0 "vector_memory_operand")) +(define_special_memory_constraint "Bc" + "@internal Constant memory operand." + (and (match_operand 0 "memory_operand") + (match_test "constant_address_p (XEXP (op, 0))"))) + (define_constraint "Bs" "@internal Sibcall memory operand." (ior (and (not (match_test "TARGET_X32")) Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 243934) +++ config/i386/i386.md (working copy) @@ -1295,7 +1295,7 @@ (define_insn "*cmpqi_ext_1" [(set (reg FLAGS_REG) (compare - (match_operand:QI 0 "nonimmediate_operand" "Q,m") + (match_operand:QI 0 "nonimmediate_operand" "QBc,m") (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q") @@ -1340,7 +1340,7 @@ (match_operand 0 "ext_register_operand" "Q,Q") (const_int 8) (const_int 8)) 0) - (match_operand:QI 1 "general_operand" "Qn,m")))] + (match_operand:QI 1 "general_operand" "QnBc,m")))] "ix86_match_ccmode (insn, CCmode)" "cmp{b}\t{%1, %h0|%h0, %1}" [(set_attr "isa" "*,nox64") @@ -2781,7 +2781,7 @@ (set_attr "mode" "SI")]) (define_insn "*extvqi" - [(set (match_operand:QI 0 "nonimmediate_operand" "=Q,?R,m") + [(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m") (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q,Q") (const_int 8) (const_int 8)))] @@ -2836,7 +2836,7 @@ (set_attr "mode" "SI")]) (define_insn "*extzvqi" - [(set (match_operand:QI 0 "nonimmediate_operand" "=Q,?R,m") + [(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m") (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q,Q") (const_int 8) @@ -2897,7 +2897,7 @@ [(set (zero_extract:SWI248 (match_operand 0 "ext_register_operand" "+Q,Q") (const_int 8) (const_int 8)) - (match_operand:SWI248 1 "general_operand" "Qn,m"))] + (match_operand:SWI248 1 "general_operand" "QnBc,m"))] "" { if (CONST_INT_P (operands[1])) @@ -6087,7 +6087,7 @@ (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "Qn,m")) 0)) + (match_operand:QI 2 "general_operand" "QnBc,m")) 0)) (clobber (reg:CC FLAGS_REG))] "" { @@ -7889,7 +7889,7 @@ (zero_extract:SI (match_operand 0 "ext_register_operand" "Q,Q") (const_int 8) (const_int 8)) 0) - (match_operand:QI 1 "general_operand" "Qn,m")) + (match_operand:QI 1 "general_operand" "QnBc,m")) (const_int 0)))] "ix86_match_ccmode (insn, CCNOmode)" "test{b}\t{%1, %h0|%h0, %1}" @@ -8417,7 +8417,7 @@ (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "Qn,m")) 0)) + (match_operand:QI 2 "general_operand" "QnBc,m")) 0)) (clobber (reg:CC FLAGS_REG))] "" "and{b}\t{%2, %h0|%h0, %2}" @@ -8435,7 +8435,7 @@ (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "Qn,m")) + (match_operand:QI 2 "general_operand" "QnBc,m")) (const_int 0))) (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q,Q") (const_int 8) @@ -8804,7 +8804,7 @@ (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "Qn,m")) 0)) + (match_operand:QI 2 "general_operand" "QnBc,m")) 0)) (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" "{b}\t{%2, %h0|%h0, %2}" @@ -8914,7 +8914,7 @@ (zero_extract:SI (match_operand 1 "ext_register_operand" "0,0") (const_int 8) (const_int 8)) 0) - (match_operand:QI 2 "general_operand" "Qn,m")) + (match_operand:QI 2 "general_operand" "QnBc,m")) (const_int 0))) (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q,Q") (const_int 8) Index: testsuite/gcc.target/i386/pr78904-3.c =================================================================== --- testsuite/gcc.target/i386/pr78904-3.c (nonexistent) +++ testsuite/gcc.target/i386/pr78904-3.c (working copy) @@ -0,0 +1,42 @@ +/* PR target/78904 */ +/* { dg-do assemble } */ +/* { dg-options "-O2" } */ + +typedef __SIZE_TYPE__ size_t; + +struct S1 +{ + unsigned char pad1; + unsigned char val; + unsigned short pad2; +}; + +extern struct S1 t[256]; + +struct S1 test_and (struct S1 a, size_t i) +{ + a.val &= t[i].val; + + return a; +} + +struct S1 test_or (struct S1 a, size_t i) +{ + a.val |= t[i].val; + + return a; +} + +struct S1 test_xor (struct S1 a, size_t i) +{ + a.val ^= t[i].val; + + return a; +} + +struct S1 test_add (struct S1 a, size_t i) +{ + a.val += t[i].val; + + return a; +}