From patchwork Mon Nov 28 23:24:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 700216 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tSN7K3zlpz9vDr for ; Tue, 29 Nov 2016 10:24:43 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="txSYu25U"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=NMrZfJj0ltgjTf5ySTpn+fW3u+n7cIzjKNMtXpF9G8CFwL T7iw7uSnhuUk7vs9lGyMMRAKOG4d1gst1jtYsKk250ZrxnNBGnIq/OVowFESXmXl Az1GH7MLdQvycqAOyU8TYHdfWuS2I+s1m5Yv/+JAFosO4Aq8GrzWvtqJcH2Vo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=bmsAcOYIk8AY0GxkJ3UZnw1EdOQ=; b=txSYu25UQt3ALoP4ht5T Oc613Jv//y7WhFfww/J+AraJNSlR7iS0Zd1kTqK9GYsdusP+WcWI/r1GOWlOVoQ5 7aQNYS+Xg95I6QAWg01BlvYoktOp3KWs8S/bvX2HiEbYVp8/xeaGlPAb4fXAiQ3I Uq1vQDwonzUr1Bdd223ewCI= Received: (qmail 5892 invoked by alias); 28 Nov 2016 23:24:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5696 invoked by uid 89); 28 Nov 2016 23:24:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.0 required=5.0 tests=AWL, BAYES_50, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=DImode, dimode, 0, 0, 0, simode X-HELO: mail-vk0-f54.google.com Received: from mail-vk0-f54.google.com (HELO mail-vk0-f54.google.com) (209.85.213.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 28 Nov 2016 23:24:15 +0000 Received: by mail-vk0-f54.google.com with SMTP id w194so82637538vkw.2 for ; Mon, 28 Nov 2016 15:24:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=lCsYN+wYSgn2RJ2llauUO3wqqwtOCFGOz7WToRUYANc=; b=YRhFhWg1WkCanfkXbB6eOCNC85y7Nck5eXv4kcxdYIMwugGXBxBSp5hHiUnISPufRS lyOXBXIgPC2ihfa3YQyPaDVFTZeXlFKEJZYvKOau+IQLTa91fUHsRq1XRYPaiOruI8dY GT9tNCj5H7DK2Yk/XJf8V51aziF8vZs/tB8vtX3sbHH/p1A6tCuzd8x3UYX+4AcWC1oa Hi6OWNSkyhXemKLF000/Uix8a+Sctw9JYXNlkqZDDsSphkerepIjCCGj0IBlq/kmSbcS V0pugEjru0y/vNMuYbYcuqt0jOCU0RgOsI14mMtKiX7WyljIeupnUlJ/4g6ThJ+A3erT DxSw== X-Gm-Message-State: AKaTC01ABtoQ+COUTZ23Hro2RzTjpbV9Aw5Al26YVvM1cjqzaQyFGBYYeqT8aGSjfTPvq1xbojmdiGMPou6law== X-Received: by 10.31.135.199 with SMTP id j190mr9050034vkd.62.1480375444741; Mon, 28 Nov 2016 15:24:04 -0800 (PST) MIME-Version: 1.0 Received: by 10.103.83.67 with HTTP; Mon, 28 Nov 2016 15:24:04 -0800 (PST) From: Uros Bizjak Date: Tue, 29 Nov 2016 00:24:04 +0100 Message-ID: Subject: [PATCH, i386]: Macroize and cleanup some AND patterns To: "gcc-patches@gcc.gnu.org" No functional changes. 2016-11-28 Uros Bizjak * config/i386/i386.md (*and_1): Merge insn pattern from *andsi_1 and *andhi_1 using SWI24 mode iterator. Use multi-line output template string. (*anddi_1): Use multi-line output template string. (*andqi_1): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 242925) +++ config/i386/i386.md (working copy) @@ -8172,20 +8172,11 @@ (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)" -{ - switch (get_attr_type (insn)) - { - case TYPE_IMOVX: - return "#"; - - default: - gcc_assert (rtx_equal_p (operands[0], operands[1])); - if (get_attr_mode (insn) == MODE_SI) - return "and{l}\t{%k2, %k0|%k0, %k2}"; - else - return "and{q}\t{%2, %0|%0, %2}"; - } -} + "@ + and{l}\t{%k2, %k0|%k0, %k2} + and{q}\t{%2, %0|%0, %2} + and{q}\t{%2, %0|%0, %2} + #" [(set_attr "type" "alu,alu,alu,imovx") (set_attr "length_immediate" "*,*,*,0") (set (attr "prefix_rex") @@ -8221,24 +8212,18 @@ [(set_attr "type" "alu") (set_attr "mode" "SI")]) -(define_insn "*andsi_1" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya") - (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm") - (match_operand:SI 2 "x86_64_general_operand" "re,rm,L"))) +(define_insn "*and_1" + [(set (match_operand:SWI24 0 "nonimmediate_operand" "=rm,r,Ya") + (and:SWI24 (match_operand:SWI24 1 "nonimmediate_operand" "%0,0,qm") + (match_operand:SWI24 2 "" "r,rm,L"))) (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (AND, SImode, operands)" -{ - switch (get_attr_type (insn)) - { - case TYPE_IMOVX: - return "#"; - - default: - gcc_assert (rtx_equal_p (operands[0], operands[1])); - return "and{l}\t{%2, %0|%0, %2}"; - } -} + "ix86_binary_operator_ok (AND, mode, operands)" + "@ + and{}\t{%2, %0|%0, %2} + and{}\t{%2, %0|%0, %2} + #" [(set_attr "type" "alu,alu,imovx") + (set_attr "length_immediate" "*,*,0") (set (attr "prefix_rex") (if_then_else (and (eq_attr "type" "imovx") @@ -8246,36 +8231,8 @@ (match_operand 1 "ext_QIreg_operand"))) (const_string "1") (const_string "*"))) - (set_attr "length_immediate" "*,*,0") - (set_attr "mode" "SI")]) + (set_attr "mode" ",,SI")]) -(define_insn "*andhi_1" - [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,Ya") - (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm") - (match_operand:HI 2 "general_operand" "rn,rm,L"))) - (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (AND, HImode, operands)" -{ - switch (get_attr_type (insn)) - { - case TYPE_IMOVX: - return "#"; - - default: - gcc_assert (rtx_equal_p (operands[0], operands[1])); - return "and{w}\t{%2, %0|%0, %2}"; - } -} - [(set_attr "type" "alu,alu,imovx") - (set_attr "length_immediate" "*,*,0") - (set (attr "prefix_rex") - (if_then_else - (and (eq_attr "type" "imovx") - (match_operand 1 "ext_QIreg_operand")) - (const_string "1") - (const_string "*"))) - (set_attr "mode" "HI,HI,SI")]) - (define_insn "*andqi_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") @@ -8282,18 +8239,10 @@ (match_operand:QI 2 "general_operand" "qn,qmn,rn"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (AND, QImode, operands)" -{ - switch (which_alternative) - { - case 0: - case 1: - return "and{b}\t{%2, %0|%0, %2}"; - case 2: - return "and{l}\t{%k2, %k0|%k0, %k2}"; - default: - gcc_unreachable (); - } -} + "@ + and{b}\t{%2, %0|%0, %2} + and{b}\t{%2, %0|%0, %2} + and{l}\t{%k2, %k0|%k0, %k2}" [(set_attr "type" "alu") (set_attr "mode" "QI,QI,SI") ;; Potential partial reg stall on alternative 2.