From patchwork Thu Jan 28 22:43:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 574949 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C1702140C17 for ; Fri, 29 Jan 2016 09:44:13 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=go12dPrU; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:cc:content-type; q=dns; s=default; b=QUvV+Xo9D1ZE+csiFiSj/UthCNhQoWtXXAJukvWfu+R 81jKTbgA0hWp2WIN3bzLpkkP1KnKNI5HyTwc6E4LqR2hYA5ytnOy4hI8NsfRQsjw ucS941qSHMPMtQoai5b13IU3O8tP+HVD6jwfYHAfBlqtwdVZUgNrZL7pADG+k0ik = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:cc:content-type; s=default; bh=AWu//3m28DBtDOvUcwDoUBpegh4=; b=go12dPrURsoHmjmMO pCnu6T7BrUIDOd27QZdnUjEQl8M5m//UMbpQC65MPxQm5r9sgI/+RS77HWJUZZH+ /NI5tAc776VROmuFmrHDL6B4fS2sR3kpqOfNuCUQ45aEZx7k+Wz4tPV2XLkGisa5 E93VUlug4jWu1gyTxolPHve+CY= Received: (qmail 113313 invoked by alias); 28 Jan 2016 22:44:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 113286 invoked by uid 89); 28 Jan 2016 22:44:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=no version=3.3.2 spammy=backported, 1527, 1526, 152, 7 X-HELO: mail-oi0-f53.google.com Received: from mail-oi0-f53.google.com (HELO mail-oi0-f53.google.com) (209.85.218.53) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 28 Jan 2016 22:43:57 +0000 Received: by mail-oi0-f53.google.com with SMTP id r14so36510469oie.0 for ; Thu, 28 Jan 2016 14:43:56 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:date:message-id:subject:from:to:cc :content-type; bh=pD4G/vWhzQ253VcdXeSwcIhQFQmeZwzDuUn8oYCqp/U=; b=b8Qb66ARa7Gkqzd1dZehHuwYd30kGPH2gDhrrt8lq8fviFvx3TUM5o5m3c7irNMweU HKEM0vLVNnMU4Bm/73qVJ7+IuTGjnxsqiVF3LckFlrTrtMs9mMLx3gw0TIMX1FbMG8NE tpx/lUcuSSKX8per08nnsi0Y1mIxvsLFxEcy+0RkrfiOG9fEjc3MtAepCPOhy3wMtwkU 0S3qfsi8FGUwNBQASUuep7HdeZ5xw8hxJXct84wSKYQMTLme+ahNJ1S0P4OK+npL+Qhp BWoPXRtEKbFgky9ntUa4jSSB0qyVWxej4DorI27aJLmYCilRljJAgRuzOecWmFA/HiG/ lBpg== X-Gm-Message-State: AG10YOS/H3jRdHljdH/kXY7jvcb2uA8AIS5fA2wSzFviaID4tAe/X47AV0D55g55jTl9oC1gvcSiAAVPddDyFg== MIME-Version: 1.0 X-Received: by 10.202.77.151 with SMTP id a145mr3646546oib.117.1454021035048; Thu, 28 Jan 2016 14:43:55 -0800 (PST) Received: by 10.60.143.4 with HTTP; Thu, 28 Jan 2016 14:43:54 -0800 (PST) Date: Thu, 28 Jan 2016 23:43:54 +0100 Message-ID: Subject: [PATCH, i386]: Fix PR69549, wrong code with -O2 and vector arithmetics @ x86_64 From: Uros Bizjak To: "gcc-patches@gcc.gnu.org" Cc: Jakub Jelinek Hello! Attached patch corrects "C" constraint to accept only SSE constant zero operand and introduces new "BC" constraint to accept all SSE constant operands (all bits 0 and all bits 1). As discussed in the PR, the compiler ICEs when "C" constraint is used non-zero vector operands, so it is still possible to change the constraint a bit. With fixed constraint, we get "impossible constraint" error instead of ICEing when following testcase: --cut here-- typedef int __v4si __attribute__ ((__vector_size__ (16))); void test (void) { asm volatile ("%0" : : "C" ( (__v4si) { -1, -1, -1, -1 } )); } --cut here-- is compiled with -O2 -msse2. 2016-01-28 Uros Bizjak PR target/69459 * config/i386/constraints.md (C): Only accept constant zero operand. (BC): New constraint. * config/i386/sse.md (*mov_internal): Use BC constraint instead of C constraint. * doc/md.texi (Machine Constraints): Update description of C constraint. testsuite/ChangeLog: 2016-01-28 Uros Bizjak PR target/69459 * gcc.target/i386/pr69459.c: New test. Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Patch was committed to mainline SVN and will be backported to release branches. Uros. Index: config/i386/constraints.md =================================================================== --- config/i386/constraints.md (revision 232929) +++ config/i386/constraints.md (working copy) @@ -152,6 +152,7 @@ ;; s Sibcall memory operand, not valid for TARGET_X32 ;; w Call memory operand, not valid for TARGET_X32 ;; z Constant call address operand. +;; C SSE constant operand. (define_constraint "Bf" "@internal Flags register operand." @@ -183,6 +184,10 @@ "@internal Constant call address operand." (match_operand 0 "constant_call_address_operand")) +(define_constraint "BC" + "@internal SSE constant operand." + (match_test "standard_sse_constant_p (op)")) + ;; Integer constant constraints. (define_constraint "I" "Integer constant in the range 0 @dots{} 31, for 32-bit shifts." @@ -233,8 +238,8 @@ ;; This can theoretically be any mode's CONST0_RTX. (define_constraint "C" - "Standard SSE floating point constant." - (match_test "standard_sse_constant_p (op)")) + "SSE constant zero operand." + (match_test "standard_sse_constant_p (op) == 1")) ;; Constant-or-symbol-reference constraints. Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 232929) +++ config/i386/sse.md (working copy) @@ -833,7 +833,7 @@ (define_insn "*mov_internal" [(set (match_operand:VMOVE 0 "nonimmediate_operand" "=v,v ,m") - (match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" "C ,vm,v"))] + (match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" "BC,vm,v"))] "TARGET_SSE && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" Index: doc/md.texi =================================================================== --- doc/md.texi (revision 232929) +++ doc/md.texi (working copy) @@ -4100,7 +4100,7 @@ Integer constant in the range 0 @dots{} 127, for 1 Standard 80387 floating point constant. @item C -Standard SSE floating point constant. +SSE constant zero operand. @item e 32-bit signed integer constant, or a symbolic reference known Index: testsuite/gcc.target/i386/pr69459.c =================================================================== --- testsuite/gcc.target/i386/pr69459.c (nonexistent) +++ testsuite/gcc.target/i386/pr69459.c (working copy) @@ -0,0 +1,42 @@ +/* PR target/69549 */ +/* { dg-do run { target sse2_runtime } } */ +/* { dg-options "-O2 -msse2" } */ + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +typedef unsigned long long u64; +typedef unsigned char v16u8 __attribute__ ((vector_size (16))); +typedef unsigned short v16u16 __attribute__ ((vector_size (16))); +typedef unsigned int v16u32 __attribute__ ((vector_size (16))); +typedef unsigned long long v16u64 __attribute__ ((vector_size (16))); + +u64 __attribute__((noinline, noclone)) +foo (u8 u8_0, u16 u16_3, v16u8 v16u8_0, v16u16 v16u16_0, v16u32 v16u32_0, v16u64 v16u64_0, v16u8 v16u8_1, v16u16 v16u16_1, v16u32 v16u32_1, v16u64 v16u64_1, v16u8 v16u8_2, v16u16 v16u16_2, v16u32 v16u32_2, v16u64 v16u64_2, v16u8 v16u8_3, v16u16 v16u16_3, v16u32 v16u32_3, v16u64 v16u64_3) +{ + v16u64_0 /= (v16u64){u16_3, ((0))} | 1; + v16u64_1 += (v16u64)~v16u32_0; + v16u16_1 /= (v16u16){-v16u64_3[1]} | 1; + v16u64_3[1] -= 0x1fffffff; + v16u32_2 /= (v16u32)-v16u64_0 | 1; + v16u32_1 += ~v16u32_1; + v16u16_3 %= (v16u16){0xfff, v16u32_2[3], v16u8_0[14]} | 1; + v16u64_3 -= (v16u64)v16u32_2; + if (v16u64_1[1] >= 1) { + v16u64_0 %= (v16u64){v16u32_0[1]} | 1; + v16u32_1[1] %= 0x5fb856; + v16u64_1 |= -v16u64_0; + } + v16u8_0 *= (v16u8)v16u32_1; + return u8_0 + v16u8_0 [12] + v16u8_0 [13] + v16u8_0 [14] + v16u8_0 [15] + v16u16_0 [0] + v16u16_0 [1] + v16u32_0 [0] + v16u32_0 [1] + v16u32_0 [2] + v16u32_0 [3] + v16u64_0 [0] + v16u64_0 [1] + v16u8_1 [9] + v16u8_1 [10] + v16u8_1 [11] + v16u8_1 [15] + v16u16_1 [0] + v16u16_1 [1] + v16u16_1 [3] + v16u64_1 [0] + v16u64_1 [1] + v16u8_2 [3] + v16u8_2 [4] + v16u8_2 [5] + v16u8_2 [0] + v16u32_2 [1] + v16u32_2 [2] + v16u32_2 [3] + v16u64_2 [0] + v16u64_2 [1] + v16u8_3 [0] + v16u16_3 [6] + v16u16_3[7] + v16u32_3[1] + v16u32_3[2] + v16u64_3[0] + v16u64_3[1]; +} + +int +main () +{ + u64 x = foo(1, 1, (v16u8){1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, (v16u16){1, 1}, (v16u32){1}, (v16u64){1}, (v16u8){1}, (v16u16){1, 1}, (v16u32){1}, (v16u64){1}, (v16u8){1, 1, 1, 1, 1}, (v16u16){1}, (v16u32){1}, (v16u64){1}, (v16u8){1}, (v16u16){1}, (v16u32){1}, (v16u64){1}); + + if (x != 0xffffffffe0000209) + __builtin_abort(); + return 0; +}