From patchwork Tue Feb 7 10:00:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 139894 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 8557FB7204 for ; Tue, 7 Feb 2012 21:00:23 +1100 (EST) Comment: DKIM? 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See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:MIME-Version:Received:Received:In-Reply-To:References:Date:Message-ID:Subject:From:To:Cc:Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=KFOwDDL85Lmi1ZUNORfhbiJFf9rG1nCWGs0YVaMamBNXBDFPES1EIkNnTQ+3OH cfyAwoyx488xmOwB0wp+9FqsE+CDgiKz1KEub/ZypHCZki/JrzT/VwpqwvjKRJoJ reObUFf0AKnhofKgUdaAPL9RpNxneOH0boBqxzU0ola4A=; Received: (qmail 982 invoked by alias); 7 Feb 2012 10:00:19 -0000 Received: (qmail 964 invoked by uid 22791); 7 Feb 2012 10:00:17 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, TW_VZ, TW_ZB, TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-yx0-f175.google.com (HELO mail-yx0-f175.google.com) (209.85.213.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 07 Feb 2012 10:00:04 +0000 Received: by yenr5 with SMTP id r5so2982532yen.20 for ; Tue, 07 Feb 2012 02:00:03 -0800 (PST) MIME-Version: 1.0 Received: by 10.236.93.4 with SMTP id k4mr29983415yhf.114.1328608803408; Tue, 07 Feb 2012 02:00:03 -0800 (PST) Received: by 10.146.124.2 with HTTP; Tue, 7 Feb 2012 02:00:03 -0800 (PST) In-Reply-To: References: <4F303F26.6050705@redhat.com> Date: Tue, 7 Feb 2012 11:00:03 +0100 Message-ID: Subject: Re: [PATCH 4.8, i386]: Enable post-reload compare optimization pass (PR28685) From: Uros Bizjak To: Richard Henderson Cc: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Mon, Feb 6, 2012 at 10:30 PM, Uros Bizjak wrote: >> Hmm.  Well, the only thing that's going to work for x86 is the double-compare >> elimination portion. >> >> If we want to use this pass for x86, then for 4.8 we should also fix the >> discrepancy between the compare-elim canonical >> >>  [(operate) >>   (set-cc)] >> >> and the combine canonical >> >>  [(set-cc) >>   (operate)] >> >> (Because of the simplicity of the substitution in compare-elim, I prefer >> the former as the canonical canonical.) > > You are probably referring to following testcase: > > --cut here-- > int test (int a, int b) > { >  int lt = a + b < 0; >  int eq = a + b == 0; >  if (lt) >    return 1; >  return eq; > } > --cut here-- > > where combine creates: > > Trying 8 -> 9: > Successfully matched this instruction: > (parallel [ >        (set (reg:CCZ 17 flags) >            (compare:CCZ (plus:SI (reg/v:SI 63 [ a ]) >                    (reg/v:SI 64 [ b ])) >                (const_int 0 [0]))) >        (set (reg:SI 60 [ D.1710 ]) >            (plus:SI (reg/v:SI 63 [ a ]) >                (reg/v:SI 64 [ b ]))) >    ]) Attached patch teaches combine to swap operands of a double set pattern and retries recognition. Also added are minimum target-dependant changes to handle the testcase above. Unfortunately, compare elimination was not able to remove redundant compare, although the testcase is carefully crafted to require only sign flag to be valid. Following enters compare-elim pass: (insn 9 8 10 2 (parallel [ (set (reg:SI 5 di [orig:60 D.1710 ] [60]) (plus:SI (reg/v:SI 5 di [orig:63 a ] [63]) (reg/v:SI 4 si [orig:64 b ] [64]))) (set (reg:CCZ 17 flags) (compare:CCZ (plus:SI (reg/v:SI 5 di [orig:63 a ] [63]) (reg/v:SI 4 si [orig:64 b ] [64])) (const_int 0 [0]))) ]) cmp.c:4 261 {*addsi_2} (nil)) (note 10 9 33 2 NOTE_INSN_DELETED) (insn 33 10 34 2 (set (reg:QI 1 dx [65]) (eq:QI (reg:CCZ 17 flags) (const_int 0 [0]))) cmp.c:4 595 {*setcc_qi} (nil)) (insn 34 33 30 2 (set (reg:SI 1 dx [65]) (zero_extend:SI (reg:QI 1 dx [65]))) cmp.c:4 123 {*zero_extendqisi2_movzbl} (nil)) (insn 30 34 29 2 (set (reg/v:SI 0 ax [orig:59 eq ] [59]) (const_int 1 [0x1])) cmp.c:6 64 {*movsi_internal} (expr_list:REG_EQUAL (const_int 1 [0x1]) (nil))) (insn 29 30 31 2 (set (reg:CCGOC 17 flags) (compare:CCGOC (reg:SI 5 di [orig:60 D.1710 ] [60]) (const_int 0 [0]))) cmp.c:6 2 {*cmpsi_ccno_1} (nil)) (insn 31 29 25 2 (set (reg/v:SI 0 ax [orig:59 eq ] [59]) (if_then_else:SI (ge (reg:CCGOC 17 flags) (const_int 0 [0])) (reg:SI 1 dx [65]) (reg/v:SI 0 ax [orig:59 eq ] [59]))) cmp.c:6 903 {*movsicc_noc} (nil)) The resulting code still includes redundant test that sets sign flag: test: addl %esi, %edi movl $1, %eax sete %dl >> testl %edi, %edi movzbl %dl, %edx cmovns %edx, %eax ret (BTW: I think that the change to combine.c would be nice to have, to find more other combine opportunities. I will propose the patch separately.) Uros. Index: combine.c =================================================================== --- combine.c (revision 183953) +++ combine.c (working copy) @@ -10687,6 +10687,30 @@ recog_for_combine (rtx *pnewpat, rtx insn, rtx *pn print_rtl_single (dump_file, pat); } + /* If PAT is a PARALLEL with two SETs, swap the SETs and try again. */ + if (insn_code_number < 0 + && GET_CODE (pat) == PARALLEL + && XVECLEN (pat, 0) == 2 + && GET_CODE (XVECEXP (pat, 0, 0)) == SET + && GET_CODE (XVECEXP (pat, 0, 1)) == SET) + { + rtx set0 = XVECEXP (pat, 0, 0); + rtx set1 = XVECEXP (pat, 0, 1); + + SUBST (XVECEXP (pat, 0, 0), set1); + SUBST (XVECEXP (pat, 0, 1), set0); + + insn_code_number = recog (pat, insn, &num_clobbers_to_add); + if (dump_file && (dump_flags & TDF_DETAILS)) + { + if (insn_code_number < 0) + fputs ("Failed to match this instruction:\n", dump_file); + else + fputs ("Successfully matched this instruction:\n", dump_file); + print_rtl_single (dump_file, pat); + } + } + /* If it isn't, there is the possibility that we previously had an insn that clobbered some register as a side effect, but the combined insn doesn't need to do that. So try once more without the clobbers Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 183953) +++ config/i386/i386.md (working copy) @@ -5808,14 +5808,14 @@ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]) (define_insn "*add_2" - [(set (reg FLAGS_REG) + [(set (match_operand:SWI 0 "nonimmediate_operand" "=,m") + (plus:SWI + (match_operand:SWI 1 "nonimmediate_operand" "%0,0") + (match_operand:SWI 2 "" ","))) + (set (reg FLAGS_REG) (compare - (plus:SWI - (match_operand:SWI 1 "nonimmediate_operand" "%0,0") - (match_operand:SWI 2 "" ",")) - (const_int 0))) - (set (match_operand:SWI 0 "nonimmediate_operand" "=,m") - (plus:SWI (match_dup 1) (match_dup 2)))] + (plus:SWI (match_dup 1) (match_dup 2)) + (const_int 0)))] "ix86_match_ccmode (insn, CCGOCmode) && ix86_binary_operator_ok (PLUS, mode, operands)" { Index: config/i386/i386.c =================================================================== --- config/i386/i386.c (revision 183953) +++ config/i386/i386.c (working copy) @@ -17611,7 +17611,7 @@ ix86_match_ccmode (rtx insn, enum machine_mode req set = PATTERN (insn); if (GET_CODE (set) == PARALLEL) - set = XVECEXP (set, 0, 0); + set = XVECEXP (set, 0, 1); gcc_assert (GET_CODE (set) == SET); gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE); @@ -38685,6 +38685,9 @@ ix86_autovectorize_vector_sizes (void) #undef TARGET_EXPAND_TO_RTL_HOOK #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi +#undef TARGET_FLAGS_REGNUM +#define TARGET_FLAGS_REGNUM FLAGS_REG + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p