From patchwork Tue Sep 9 18:45:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xinliang David Li X-Patchwork-Id: 387424 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3F21414012B for ; Wed, 10 Sep 2014 04:45:51 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; q=dns; s=default; b=DV/rOf9RM1XXrXej+9 uTashs0/kBzUuVYhA0xvU9UlQY8fMcKiGxb2PLA+V6t2R1waCceF2Y1NKnu3+sUN bmBIfD2gKhJBnoaQytdgvrM8sD33K4M1LZXlmwgEgZVdv+gd3cXRA9EjRWnhxBLy ZNhk0bAgJ0+BbCKC5Tfp9hq+M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; s=default; bh=C/vv6TfqR7D07IICAZBsvV5X Je0=; b=sk+CXTgVpB/Kzyf480lPUE46kLJWQao5e/JojTkbuGJyU/KaF67SkTjj bKwh8OP/Td+0lVE/6gCO42APMJYZNYMKjcYbm719b6D90rFgUAqVAaWsPWFt7rFH uBjyWGoz4oYJJo1GMoPHyHdnjoeolDAkRzT14eIgTJ0xDs8CHiI= Received: (qmail 12962 invoked by alias); 9 Sep 2014 18:45:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 12951 invoked by uid 89); 9 Sep 2014 18:45:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ie0-f172.google.com Received: from mail-ie0-f172.google.com (HELO mail-ie0-f172.google.com) (209.85.223.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 09 Sep 2014 18:45:41 +0000 Received: by mail-ie0-f172.google.com with SMTP id tr6so3780022ieb.3 for ; Tue, 09 Sep 2014 11:45:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=JRlZs8L41O8luRLgw4233eM9WNB38dH7h+1Mlr6gRnY=; b=SpVKqT0wyFrBzaavN+IzxGXpts0RzwitxHYomnXPCL2pLGamBDhqzIO488EHmTSHdL 6ck2PD44u5/rFKe7sZYQ7m0cZ2jlhia5sj2VNnFsoECThsm9X/2SN6E//yiUXonE6w9x Tv6M3o1aLGN7OGY7n4OEAwxKdk0i1YtP6OfO+1l5XvJR/YNsC0a/4oh+H3KTWeIy/Mug P9IjZPeo8PaNvfXzqDrKAWXT/Vl82UHKukcrQxUaUY0cY8G/X//ipQ5vsqqh+1w9MqTi Cj9XnS+pcjpuLMf/p8x/Gz+ccYxkNdkhjms/YBv3595JhZhDHfEwaITC+vi1DQqeWKFB gkyw== X-Gm-Message-State: ALoCoQkCfT5ew4bjaQp2MwugLUKZmxl0pCboESBHjnNRGu9+mYDeQE3uXmuDLA+0rOeNxxcfh7RR MIME-Version: 1.0 X-Received: by 10.42.67.133 with SMTP id t5mr12397664ici.62.1410288339333; Tue, 09 Sep 2014 11:45:39 -0700 (PDT) Received: by 10.107.155.136 with HTTP; Tue, 9 Sep 2014 11:45:39 -0700 (PDT) In-Reply-To: <540F398A.4070705@arm.com> References: <540F398A.4070705@arm.com> Date: Tue, 9 Sep 2014 11:45:39 -0700 Message-ID: Subject: Re: [PATCH ARM] Fix PR target/63209 From: Xinliang David Li To: Richard Earnshaw Cc: GCC Patches X-IsSubscribed: yes Richard, thanks for the review. The revised patch is attached. Is this one OK (after testing is done)? David 2014-09-08 Xinliang David Li PR target/63209 * config/arm/arm.md (movcond_addsi): Handle case where source and target operands are the same 2014-09-08 Xinliang David Li PR target/63209 * gcc.c-torture/execute/pr63209.c: New test On Tue, Sep 9, 2014 at 10:31 AM, Richard Earnshaw wrote: > On 09/09/14 16:58, Xinliang David Li wrote: >> The attached patch fixed the problem reported in PR63209. The problem >> exists in both gcc4.9 and trunk. >> >> Regression test on arm-unknown-linux-gnueabi passes. >> >> Ok for gcc-4.9 and trunk? >> > > No, this isn't right. I don't think you need a new pattern here (you > certainly don't want a new insn - at most you would just need a new > split). But I think you just need some special case code in the > existing pattern to handle the overlap case. > > Also, please do not post ChangeLog entries in patch format; they won't > apply by the time the patch is ready to be committed. > > R. > > >> (I sent the patch last night, but it got lost somehow) >> >> >> David >> >> >> pr63209.txt >> >> >> Index: ChangeLog >> =================================================================== >> --- ChangeLog (revision 215039) >> +++ ChangeLog (working copy) >> @@ -1,3 +1,9 @@ >> +2014-09-08 Xinliang David Li >> + >> + PR target/63209 >> + * config/arm/arm.md (movcond_addsi_1): New pattern. >> + (movcond_addsi): Add a constraint. >> + >> 2014-09-08 Trevor Saunders >> >> * common/config/picochip/picochip-common.c: Remove. >> Index: config/arm/arm.md >> =================================================================== >> --- config/arm/arm.md (revision 215039) >> +++ config/arm/arm.md (working copy) >> @@ -9302,6 +9302,43 @@ >> (set_attr "type" "multiple")] >> ) >> >> +(define_insn_and_split "movcond_addsi_1" >> + [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") >> + (if_then_else:SI >> + (match_operator 4 "comparison_operator" >> + [(plus:SI (match_operand:SI 2 "s_register_operand" "r,r,r") >> + (match_operand:SI 3 "arm_add_operand" "rIL,rIL,rIL")) >> + (const_int 0)]) >> + (match_operand:SI 1 "arm_rhs_operand" "rI,rPy,r") >> + (match_dup:SI 0))) >> + (clobber (reg:CC CC_REGNUM))] >> + "TARGET_32BIT" >> + "#" >> + "&& reload_completed" >> + [(set (reg:CC_NOOV CC_REGNUM) >> + (compare:CC_NOOV >> + (plus:SI (match_dup 2) >> + (match_dup 3)) >> + (const_int 0))) >> + (cond_exec (match_dup 5) >> + (set (match_dup 0) (match_dup 1)))] >> + " >> + { >> + enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[4]), >> + operands[2], operands[3]); >> + enum rtx_code rc = GET_CODE (operands[4]); >> + >> + operands[5] = gen_rtx_REG (mode, CC_REGNUM); >> + gcc_assert (!(mode == CCFPmode || mode == CCFPEmode)); >> + operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[5], const0_rtx); >> + } >> + " >> + [(set_attr "conds" "clob") >> + (set_attr "enabled_for_depr_it" "no,yes,yes") >> + (set_attr "type" "multiple")] >> +) >> + >> + >> (define_insn_and_split "movcond_addsi" >> [(set (match_operand:SI 0 "s_register_operand" "=r,l,r") >> (if_then_else:SI >> @@ -9312,7 +9349,7 @@ >> (match_operand:SI 1 "arm_rhs_operand" "rI,rPy,r") >> (match_operand:SI 2 "arm_rhs_operand" "rI,rPy,r"))) >> (clobber (reg:CC CC_REGNUM))] >> - "TARGET_32BIT" >> + "TARGET_32BIT && REGNO (operands[2]) != REGNO (operands[0])" >> "#" >> "&& reload_completed" >> [(set (reg:CC_NOOV CC_REGNUM) >> Index: testsuite/ChangeLog >> =================================================================== >> --- testsuite/ChangeLog (revision 215039) >> +++ testsuite/ChangeLog (working copy) >> @@ -1,3 +1,8 @@ >> +2014-09-08 Xinliang David Li >> + >> + PR target/63209 >> + * gcc.c-torture/execute/pr63209.c: New test >> + >> 2014-09-08 Jakub Jelinek >> >> PR tree-optimization/60196 >> Index: testsuite/gcc.c-torture/execute/pr63209.c >> =================================================================== >> --- testsuite/gcc.c-torture/execute/pr63209.c (revision 0) >> +++ testsuite/gcc.c-torture/execute/pr63209.c (revision 0) >> @@ -0,0 +1,27 @@ >> +static int Sub(int a, int b) { >> + return b -a; >> +} >> + >> +static unsigned Select(unsigned a, unsigned b, unsigned c) { >> + const int pa_minus_pb = >> + Sub((a >> 8) & 0xff, (b >> 8) & 0xff) + >> + Sub((a >> 0) & 0xff, (b >> 0) & 0xff); >> + return (pa_minus_pb <= 0) ? a : b; >> +} >> + >> +__attribute__((noinline)) unsigned Predictor(unsigned left, const unsigned* const top) { >> + const unsigned pred = Select(top[1], left, top[0]); >> + return pred; >> +} >> + >> +int main(void) { >> + const unsigned top[2] = {0xff7a7a7a, 0xff7a7a7a}; >> + const unsigned left = 0xff7b7b7b; >> + const unsigned pred = Predictor(left, top /*+ 1*/); >> + if (pred == left) >> + return 0; >> + return 1; >> +} >> + >> + >> + >> > > Index: config/arm/arm.md =================================================================== --- config/arm/arm.md (revision 215039) +++ config/arm/arm.md (working copy) @@ -9328,10 +9328,16 @@ enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[5]), operands[3], operands[4]); enum rtx_code rc = GET_CODE (operands[5]); - operands[6] = gen_rtx_REG (mode, CC_REGNUM); gcc_assert (!(mode == CCFPmode || mode == CCFPEmode)); - rc = reverse_condition (rc); + if (REGNO (operands[2]) != REGNO (operands[0])) + rc = reverse_condition (rc); + else + { + rtx tmp = operands[1]; + operands[1] = operands[2]; + operands[2] = tmp; + } operands[6] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx); } Index: testsuite/gcc.c-torture/execute/pr63209.c =================================================================== --- testsuite/gcc.c-torture/execute/pr63209.c (revision 0) +++ testsuite/gcc.c-torture/execute/pr63209.c (revision 0) @@ -0,0 +1,27 @@ +static int Sub(int a, int b) { + return b -a; +} + +static unsigned Select(unsigned a, unsigned b, unsigned c) { + const int pa_minus_pb = + Sub((a >> 8) & 0xff, (b >> 8) & 0xff) + + Sub((a >> 0) & 0xff, (b >> 0) & 0xff); + return (pa_minus_pb <= 0) ? a : b; +} + +__attribute__((noinline)) unsigned Predictor(unsigned left, const unsigned* const top) { + const unsigned pred = Select(top[1], left, top[0]); + return pred; +} + +int main(void) { + const unsigned top[2] = {0xff7a7a7a, 0xff7a7a7a}; + const unsigned left = 0xff7b7b7b; + const unsigned pred = Predictor(left, top /*+ 1*/); + if (pred == left) + return 0; + return 1; +} + + +