From patchwork Fri Jul 14 00:12:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Pinski X-Patchwork-Id: 788021 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3x7tf61s04z9s78 for ; Fri, 14 Jul 2017 10:21:32 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="vsQcsH2f"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=gUIM/sMzu9dAN83e8DXfMLQwrW4n0erF11WyL7pEYR7LHg UGFqOfpZO4mltUveE9B5fe2nYda2F3EtnFdzX8vOep14VSHRR7dLwf15BCSPki2u c9fUxCKw4TGeq4jN7vE7t1HouE0kAA/9e3mncZG/N7fwbBYsmCDnGM6Am6/hY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=EXHbjrt1yM9LvEErjRvTRm6YFOc=; b=vsQcsH2f1mMpxBq3xtfZ Y5ubqAO5gTbhX37cejN1yE3dDrQrnBY99O5mqAmj6elcxfw0ag9IEabUD5+8V2Fz D+JPMqJwHdwUGnaE5Gfk6WBjYmXSkSjIfKsfWgAtQrKNJUHSUQKQ6l9leXjcxAB7 QpF7VJI7btxHuqRhpQVLrXA= Received: (qmail 52498 invoked by alias); 14 Jul 2017 00:21:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 51967 invoked by uid 89); 14 Jul 2017 00:21:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=rw, ry, yy, YY X-HELO: NAM03-BY2-obe.outbound.protection.outlook.com Received: from mail-by2nam03on0057.outbound.protection.outlook.com (HELO NAM03-BY2-obe.outbound.protection.outlook.com) (104.47.42.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 14 Jul 2017 00:21:19 +0000 Authentication-Results: gcc.gnu.org; dkim=none (message not signed) header.d=none; gcc.gnu.org; dmarc=none action=none header.from=cavium.com; Received: from mail-yb0-f172.google.com (209.85.213.172) by MWHPR07MB3422.namprd07.prod.outlook.com (10.164.206.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.13; Fri, 14 Jul 2017 00:21:16 +0000 Received: by mail-yb0-f172.google.com with SMTP id f194so28018510yba.3 for ; Thu, 13 Jul 2017 17:21:16 -0700 (PDT) X-Gm-Message-State: AIVw1111Hn8gwNL5P36sW8XjNA4uT+R2KtjMPXEWS0N8hdgRIg4zat8e wNja7GqDbdikOUO9CTkGBI7klExTow== X-Received: by 10.37.215.6 with SMTP id o6mr4999012ybg.219.1499991178939; Thu, 13 Jul 2017 17:12:58 -0700 (PDT) MIME-Version: 1.0 Received: by 10.13.223.197 with HTTP; Thu, 13 Jul 2017 17:12:58 -0700 (PDT) From: Andrew Pinski Date: Thu, 13 Jul 2017 17:12:58 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: [PATCH/AARCH64] Decimal floating point support for AARCH64 To: GCC Patches X-ClientProxiedBy: DM5PR07CA0038.namprd07.prod.outlook.com (10.168.109.24) To MWHPR07MB3422.namprd07.prod.outlook.com (10.164.206.11) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 95439c13-fc5f-452b-af38-08d4ca4e3e5a X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(300000503095)(300135400095)(49563074)(201703131423075)(201703031133081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); SRVR:MWHPR07MB3422; X-Microsoft-Exchange-Diagnostics: 1; MWHPR07MB3422; 3:u0aVqg1asEAodEyPftitu0v0ssm/zNmu35dylHMEPgwfN9w32oI+Q9W2zPmotJhdiMGwP8KV+rpcLTvqifh+VTNYYZ24G+soRGEUFKP42pUryP7YmVstSUwNdlgAw5ChjZIoBoo6USMeF2Ta0I0z7il2/Y3RLTvwIL9sUY3z11MyCETSHKzKYzznlK+7HuoIbwptuUV8/0MPfIcAeCIpmMzZ4WZ8PC2EK+jorVSaXjQ4+2029CjHMl2xQEm6k8sjmKaiCoKHnSSTUEgiEOw349gjb270GkvJEFFO47mIWT2D9sDc6835ngDCJ57UI6v5A1rfCgDaZt2eP4THsPROl8IuPrtYQla5+CV18eI2CF0fbZKUwx6tFgnL3kBn0z8A9PbKOyZ/GtRuGmSxfyndc+iUA6OOoiXs8O3gy8z6ep7TUZGJEAQV1b5MxlXlMnwFExa0EV8KhqhIC4+GBDRxPcU+34TiZVLcl9gbKoJz5Yu8VVghf7TJJnRWGYimnEdbemp/3B0/uR7da78qBro5BiOur3ygTcKrahrT+8w8bcXkU8lKGTO3nFY7zH7x9y64qnTWkevMp/PRlM+43OH+U2+BNSsbucNoNdBXakPrWoyd3weLeEdVN2A2eIHIcKPLfLag0NxafnT6h+5IeKVvzB9/R4ocpIZqp7f6zSfEM7XA2YKRCbzOe88Z7mIXn3J9FMBNg/5NPHBX6NaGyP+Ho8tD7dEq+0ttODl+r2Y37707WvG4rIhtkaUaqk2J66JV X-MS-TrafficTypeDiagnostic: MWHPR07MB3422: X-Microsoft-Exchange-Diagnostics: 1; MWHPR07MB3422; 25:0Ee1Qbbh/m/e42r/Vc/xQNrrXQF4yHTfMyxF+T28amCWSvzqBCcdHTrcLojEUbumcq4QDVpArMaZd6VRKeC7BcT4CWuS8g2/bhj6mzlhd6vUXoaeWeKC2CZhjUXmenqhKhT8WMov89JNTF2Q5+k0R9vgnrCT7t0fy5QOJ0DSDsWwgj66eYbTZlZpZCwvrXv1pEAtd2hoY5SUDp57OZuoGxDWdeaRz5EMYNbJYzLuuFEXESFHJEPN7oL3xsdq20nEF5tyZjA11jROZuzSsNZdgY6rH1jXvl1023JCwFD0QTJKazOa6V4ETyLG0Ep5dtJ9ZZJLlOylq7trI/BwB6mHZQ3sHw+swIHN0fTA7Dby+QtUVnwGkVTOuSbMYldDA75ged7nbtFAbBsasx/auJz7jPPZV8IrHQPaKnw1noeW/+yDTnb+mZVqTiBxuSULyIERhc2hfvUdtfqUFqcV4oNHwu6TCeseyyXRlTr9L00i/HJH+On4ScFTZOVVD4esvZdZHvnoRjpbNXaq07AIR6bvCQ/1yweBgz9nce7k699lwzCnOhED9ZN3jRqSzdQbGgG00kN3Th+HjMDsgt4vnB57DxCzIFLewzODhwlzzixDXx7M6GLsKCJMQ+lZpji1q/ciRs7Jr5gGSJn9aneky3+5Qo7DMQ85txKiLoF/KV1QKO9ZzEeE4z9oECBhB3F8PKGsBtzFq7odUvJbNMBOOVad4HxGzchX45anvlvyP+JvWVK8Y/BhhI3HD3h/35tJ6YE7za1SekiTNjtOS+aDGdtgETTQ3MtByZnSYbE054++wFafwSSm0VH7ZwGSG/Sqd/gMcoky7sxWEQZj/a/IX+Ki/Bg5DFHfajVG0ZqimFeEVVtgWYTM8GAcphmpyBdPh/2PCj4hV09sWEpAuX2xnu5JvbmZmjfNZrEClhdYtvGWyR8Vky03WPN1CNUh3w+yN7o6 X-Microsoft-Exchange-Diagnostics: 1; MWHPR07MB3422; 31:Fv0wEYDQfKYS2nr6shfygxQepiMIg2m30lsPS/SlSQZqKjkvwOPHnAUpWDsisaIaZgZkQrJIGhnaJ5MfZPizraebh6qsxOlciWQz9iTaKSEeRduAtSui9Hh20WHDHVki0tchRmFrSdt+uiNGHL6aQrQtv03PuXjhX4ZZPkUf5BjTgGsmrYfCcwVms8fM16pfUbd4Y7zG0magQBJEvx00FaoVZ+UgnI9g0oXG9fCmMpHRFTGb0yD6pgMBA0CiwzQiZc9Ruqn6AgWCjHVyOXnonKlJZdhuzcbuQNdri8pAK4hItB+208N2R1Zgfb5+05u1lOJafkVXOgg8edD4VR8PLdMNLvJsoIhtAgwreq5TskJXCFqERS0Ocf6hfpnvJWyy/XDwqD2kXtx7ip6SzeXd/rSiZ9frhKvuPhry5AruRolMo+l30XUtDx+yA4wT/75yJkqVVHIIrh90CmMurkG4EEtYO9TEdxbHqGoTje0D7pLCydN0bPwE16iLQpcUitOeXVdJDSTstHpQ5OkO2+v+t5ungCEZI2i5fCVsPB2KW8gzbjPRp81cqtuBdKaebU/NgnN1+pC+cQUFonAjSUc/KhOZLvd9rq2mlEB8Ehx3Opd5dDbIqX+qEZpKFL8vOyZQ6e4BYSREoLi1aDg8GXujaUpx816AAU9hDpKaOQ0G0NeuuXXB+po729BI1+tFn3iFhwNjhiXUjVCoqSPykd9FOLFgEK6utivryPvmQgExJSgbkVGEjrJMODbMCTQvPsHa X-Microsoft-Exchange-Diagnostics: 1; MWHPR07MB3422; 20:MmRiCXSM8pSuD/zqyk6XoVIngJyl9cbwZOEr/mlyusna1pTFkJxxaobWGQac9igR5aPERh8lQkLtY4F6iuAw9xA3fQLtsth8u9csxWFs4BDkzqv4S1nyViE/cZO7vVTyUA/81EvGj5tx2V+nIA4v2MR49S6YUTSlfDSGoGgZElPvXQo/Zc+1yhQib+OBjcwPpER5Y77uKeO2G4Fztrgdh1mAnTbN3WkNyEp5BA1BLy80fJF3A8lbdvWXwWgjnTK8gMkM1WC9jWRBVtYA3fMZesscjvkCpALivyfy95QclxC0mONzWwKUFPAW5tAWrrzZm1DCtmNjV5y3oyzbqsrY+5a4qlAOYSqdlLXjmRjQyqKSLTLzRCxaAkbuh0d55u3cN0t2ESWHKo5X4dQX5RIzCMxWmHEDt7DoGk9JP1FE8XhkzYnCmXOvc6ee8z3h2PG0mwNz1+SwUIp+B/2eR3AU/qTr//DaopXnayAbmKbAEtZ06KVkIvh+2gvEVQjxqEke X-Exchange-Antispam-Report-Test: UriScan:(133145235818549)(236129657087228)(148574349560750); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(102415395)(6040450)(601004)(2401047)(5005006)(8121501046)(2017060910075)(93006095)(93001095)(100000703101)(100105400095)(10201501046)(3002001)(6041248)(20161123562025)(20161123564025)(20161123555025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123560025)(20161123558100)(6072148)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:MWHPR07MB3422; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:MWHPR07MB3422; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; MWHPR07MB3422; 4:BtUk5vt0p4v+hlIRrxlQRdhctXly9bwACe3FegspBx?= =?us-ascii?Q?riAUR56f6Z5HPytucPRwDHKmIgRJRnEPjbSWaXFOOfs8WQkna7Gbx1rqzjfI?= =?us-ascii?Q?vqdPbpMbVm91SdPITHs8vETxNVr3/s1fsrXGF/ypmJbClx00fWJWL1Mz/aXb?= =?us-ascii?Q?//wmP3Kw1QI+Pc/q0MDgNG1FhbAU4YPoy3V3MQSfsE05Z8J86KOipyTir0BO?= =?us-ascii?Q?1DaMofxEx42WoEZd8/1bIDOl9zy2hMlYlFmfSF73bzEKOaELoFEdk9INmIgd?= =?us-ascii?Q?jpxRwz1+6mBuJI/GTXXwuUBRtA+ApiMRV2996JR4MWaOpLjPwiJmV7/wgajq?= =?us-ascii?Q?bRGt9E8lAJx+jNA3Pp+Olt1WL2zjZ32oIYAjt0IzoPJgN5VsNUhHJWBNZyOS?= =?us-ascii?Q?RQTQGi+2Bgx4FscIHg+o0YFUuwta3lejhE7UKe2OjnuOEBtMFpS5NHcrnlPj?= =?us-ascii?Q?tqWp5re3fv8/wTlcphaWpVAGXlhBASkZPL/wWG8I7qO8jjEsvaQ3SmUvSsC4?= =?us-ascii?Q?pn+/0JkpFUCibt6iIZ/506aLmhvwset+b7fmuQsTYnUpa5efjcwd2K4WasNB?= =?us-ascii?Q?DtWVRFLQ+KC/8NEYx3sp81AO6qqzeSZ8SBN60jLYYon+vScPBdw9Pp5ib5PY?= =?us-ascii?Q?tH8cy8DhXRfRofB8oa3Wj99EuYImXRPKo1FucvzJV4kPmkNBeuLrmZIBG7JT?= =?us-ascii?Q?NON5mXwHpV6DNafXO9j0anDWplNHtbtZrNyQkVUnfzh0eyEkQ9q8OPxiwnCd?= =?us-ascii?Q?/RSH+723ZUkdfhKIGjZ8yQOzDfWJUSf3zW5Ql3S2idIlLlVzo+0PWfhn5dcg?= =?us-ascii?Q?UdYkQLS2lR5qEmor7UIxzgMCTrZ4z4hk+vdwDvLzIZYcR4qvj7QJ1fDtarPX?= =?us-ascii?Q?oQHvv61uqcGI0NHTG7SF+nQM7qYIFBhtLt5vcrEQOHTH/YGpF6Bv7MkAGuog?= =?us-ascii?Q?PVOdOBWCxYgGTanqe+GFtrA0CK7mQtbDBu28k5wHUj82VgvtCzCGyKTfMgh7?= =?us-ascii?Q?DLSZpdeiCOUY1tYCZTR1/936yvnywrC1vLb4khOZAN0zcifCmjmHjWfBiAWE?= =?us-ascii?Q?eO/kvAepSgDY+/rwsU1Kwct8IYQLtRuHlhY4DBci489uFQmj93elZuxdKgru?= =?us-ascii?Q?oSMCC04cGAjzSbxmiEM0KCRqhW586EzJ1TdimRytqgixatRtyV9Rjk/hYHXN?= =?us-ascii?Q?sGddm426CP9wH/TijLhZeq+fdYAyc5AIlXHL/OhLg9bZi4N4o+eJWZKGcE52?= =?us-ascii?Q?Nfmo2zPGTQZUgDth1VITmVRUE3IhpWHVk3b2DE6ZzALEdBIrS3EE7prGbJhP?= =?us-ascii?Q?yjXnR37MsbOMTKLgSYm6o=3D?= X-Forefront-PRVS: 0368E78B5B X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(7370300001)(4630300001)(6009001)(39410400002)(39450400003)(39860400002)(39840400002)(39400400002)(39850400002)(9686003)(512954002)(7736002)(6116002)(3846002)(478600001)(72206003)(8576002)(305945005)(7350300001)(61726006)(81166006)(84326002)(5890100001)(9896002)(2906002)(21480400002)(66066001)(98316002)(53936002)(5660300001)(59536001)(2476003)(55446002)(498394004)(42186005)(189998001)(568964002)(122856001)(110136004)(8676002)(512874002)(6916009)(4610100001)(38730400002)(61266001)(54356999)(93516999)(50986999)(63696999)(55456009); DIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR07MB3422; H:mail-yb0-f172.google.com; FPR:; SPF:None; MLV:sfv; LANG:en; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; MWHPR07MB3422; 23:MU+jYJIlnSYY0nv2Mg8N+R7iiQ9j2+rrn/sYEyPfZ?= =?us-ascii?Q?AlIAxPMoUG8w3MYKDZMc2F+jTaQulvZ+pWJ7bCgyVRwEs+xzpp50TrzmMbc/?= =?us-ascii?Q?TF4yXa9Pi43l15Ivbjux9QghzqpZBJUIUk1SmWH5SFUw7UpHfj4qNOzFR7Ax?= =?us-ascii?Q?ElrJnD1RhgqzoPpmzbJZJCvfCX7Md/eHZcVjIQo8RHSby02AfLljWqRHLZs8?= =?us-ascii?Q?XFnuh3mkx3PPXx+3/kVFconclPTNpH8HwAIn2rxLvtK5d8pp/KTjh9FeXTbC?= =?us-ascii?Q?4xv/LtXy7ImMMG5VWvhOdoPPLHiT05s0JFiuxrICNccbAQW05fU9uooLbnNI?= =?us-ascii?Q?gCvU74d+2FL+NsEHz4oHCy0rUKrNXlhtcGOyhgt3dTVW5DhRgHrLteuXWS50?= =?us-ascii?Q?hjOtW7at0AyR1P8nhRKOlkrJQIHDKL2v3i6j0AIRVP/g15ABRemExhrfFu8T?= =?us-ascii?Q?DCm916c1Bm4yEnPAHxMPsw63v+ae4PcNh8FRzAcEiSkEB3FXWXUOrFN5G4+k?= =?us-ascii?Q?8I3YNyUbtr7rg14YHLHwVShtPBLMGAfztRjp4LWgYRi013rmwOFO0rgilAcl?= =?us-ascii?Q?7XOgvBNSqaJSZ1ftuj0RkmL+eSXdH3GJnykcJijbIteEEvT+O5VPF6mebrNH?= =?us-ascii?Q?N23bR3a9JvwPY1fxyYNeaejJEIvnfXzRtvJgc0b78fzJptXVo2XnEdvlPkHK?= =?us-ascii?Q?OjPY9EnBKHbXspHz5MEJfxeth0H0rqu/VQvyqDi/AipjqimvYpVmg33A4gpQ?= =?us-ascii?Q?H3YFDzvOklh/tdc0pGz87w52S02MImr9ECwQhjMpPStxYmAt6SEreUG1gqF5?= =?us-ascii?Q?8VaUaCaayzsw+0DpGGrfmh9eQ5w8z82ydkZAm1RVvWSEl2dlW5FUeeSjN43c?= =?us-ascii?Q?OZIb7g+yfDnPN86eP7XEGjnP9Or85VnYyaCaUnmfxdUM0uQ+e+psb5rm/bgV?= =?us-ascii?Q?hZ7GBH1RjEgskpjOMwaNhRDEvy/6QTxaoYLl+HS2DjBik1/w6WNVwsELBWg3?= =?us-ascii?Q?F+uMqWrFFEf0puzpleU9RmMWk7M/1N4slrNknyIPH4mz7toZqE936dOzeAB6?= =?us-ascii?Q?Du8h1A2nbIc0p2BYynZ1FrMJmmDv5+N7tE8yHNWhYYzSPhwb7vaem22zqPOt?= =?us-ascii?Q?c9rsi6AcRnaCmePy7Y6yyDk8NmGS1ompcO4vAzMBw3pwJIsGBRebUfPhXUnH?= =?us-ascii?Q?9sFO29Zb5e9s8Ifiuh+xpXWGVkYGYvJtGZwZxuFJf9xgiNg3yAHGcc3tHuaf?= =?us-ascii?Q?dvukMhddGYGcZ0Ulvk5BomreoKOH168yWG+mJ5j?= X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; MWHPR07MB3422; 6:k/w5Hfe1H9c+6CezVY665V3MRvTxyN+ak++hxNfp3A?= =?us-ascii?Q?R8roz77uFtBJoJzavuYXWGkSHZq/PCYy3vzrBzXgNeZ1xpNmETXxXeQnqO1j?= =?us-ascii?Q?PPbt/mHXSyPHxlzyfjw0juCahPkjsS7u5x0depa3gZc7JDgd3v5A4h2lAE7v?= =?us-ascii?Q?1+QjHjiUT/1fe0ihXS/6Nm0uBFVxu046tK7LZ2M3lHFY4+umxqpDPaBFaFcV?= =?us-ascii?Q?bnxwBDGnGX0TP3h0clSnCSwpQ0Cw/u5bFJAFP00tGkCyzhU0BEUBqwP8aJXl?= =?us-ascii?Q?8S9GuE+1JddDw3xWjVleBtxfHNR/DUmOOWqQPLWkhJbbFrV/Zd+BEqWYYwAq?= =?us-ascii?Q?NyB2H6qL1oOGdMsOigc6lgI10CPPhXT1bupFFAzmz3zWSuRiSojCjMr7HV5E?= =?us-ascii?Q?4wMEhvTAg8ptkBZrkWUWheXH7u+hAcTiX+hMxhpeXv4Mk8qoQW+bLJXfokMz?= =?us-ascii?Q?2wiV+oEXLun5Y07SWzhtGjERPHgn7UiYzSg7QEgeJ2cidJtEsntU54KMzIUX?= =?us-ascii?Q?pYW0WsqvGKEdhAKJhFxB1B0Npry9EQETo2a/fXgW2LJQ0ZlryJ19dZ3Yuobv?= =?us-ascii?Q?OcORVhApUzd8C/PGL+mRAOdUAacUWVxtf8rAaoPPqqWGOCsYUqSOly5slocp?= =?us-ascii?Q?rFpezevotETX/K8+tK6LorFBLMSJCLb1HI43mMVW4rV8+cfzXrcTUV0W+iJA?= =?us-ascii?Q?pbICfWFYdFVNimQZtaVkNF/rvvPpoRmPL9iaSFLd2iqByo47xkUqkzFg+BhB?= =?us-ascii?Q?AdQZwWbwwkGcTG03MWGlQLqAXn3Fq4h8BS8VWtN6efQorZAsUUdYE24S68Bm?= =?us-ascii?Q?lhNhEcITxusb2v8ep4kGWMYchFsu6h4d3nurCBYKqnnFxGRA6FmgXcP6JngP?= =?us-ascii?Q?oVZdG/8qALzOVFtqIen53GshVSitZBeGqmXd2RaUfyzooDpivKeUlGu42+UW?= =?us-ascii?Q?yNLRPUdDdD1Er1Qlw8BW9R2tiTK70CYmYX6pJUexYI6vFu96KirAZxPkjKLA?= =?us-ascii?Q?w=3D?= X-Microsoft-Exchange-Diagnostics: 1; MWHPR07MB3422; 5:7Am37sXMSBARNk+6odbK3s7g6euvbvPV9OH/seRNZzaNSA21a7eWTA7e7JDfQnPmmAS0Qdm4MX17+vDWgclPDkMOAuyXbcDG/aS2cvWMCujJ4E5YaK21AeqA9+Tf/tMqomCD3KnNXV4OeIWftJhqrjjq0+YiblKH7VsiD9uvJ6gbpVLlnDp9aKLJZKY2Q7E3hPhJ2pCeduWZyJjT4AaI6/pXRZzLiCMZCNOVnRXaCCkQ/Uyv3T6BScySTfrb2kq5z90Nbc771CGahpAChZ1O40JtsGm0ShvMZ6cxLYWGAYPv2VFyN7qeL2kfaqqCA72CiNZBNychwoLS8mehkkpn9auGK3HerXPvgOyAEWPIhQkvl9TqezOTWBwsa/XvOl1WY118MgVz0paaKJZELAJxKWvNCs/okmJneMnD1J+EbawHFdEqAKJuMMeQ1CnWH9VwJoDcAiRZLp6OGXkgBn7NVx3JnDKAbg72HSo5w7M7KodsmiGzmNtMxTwGx/j36B9J; 24:ZPYYAranwc5hPCqDhvmn4BB+ENaTi5hcOv7we8JMzfKoRbD+0XHPgtbIp4rwYM08Pa6M/TUyT6WRenZgY05UEaoriCugcoIDEOvInqt5c8Y= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; MWHPR07MB3422; 7:r06q7ushiUUuKwRsWUGvQ+dc5JM/Vlc94GmdcgddvI9KM/HbOP1zCKsdmeH1uZ+E5Rz+xKlemWTnGdA9PCioy85KTDH54EJ1BAZLsg1O1biEksmSWBuCq6lurfEZzNiG4XhNvpbhczUCcr7lvzaCGCmAbW8X/PrGKws2GOBZO6ZVghUQJYpIaJuqVfCxyuoXiodLl0dGvGGaAHc426SheNykw0Nuksq9Cdc9k0RTw1vHndutkE0/Hwx3G3O+GR8K1VRPP4627qSLSJn/enoEwDAfinJJnxSLRdu2aaeqWOJRiI1bnNWr7UrJPBAp2l4K2ATVtliCoQq9+cR4uMX70kNASLqChuZyPaaoOrooyZXP50WlSeSdBYko9D7fXj2yjSY2yNaDCezNX1gx4b34na6PIHQEOQ9D4Rdv4NhS4aEF2IpuDtcxGJlYsU4THLYwHV2mkBXDzyKiHURktd5afCGqvw2kTde+AuuG77RHr1WhVCm/mypGEPsjx1j7Usl2b87F4pNDu0PZYiGj/AeeK4d+VheM4sHEheewRlEW2pXPA3u15j4T2BktmL52/ikLkXCt8YGLPeHdYwBmt6ltgTm22gjmTzj30kW0QuXxqQ6omPLm0/xGjT8lcQKsB0uGxioOk4vHBt6E30v5sMBkE79m4X0LMVeN+fhrc71O0SaSatVGOsedv4ImESahtNaEl7/+x09OAprRske6EbXjH8Q64ZxMp/emlLCyNlwICE8mZFA0EZyqdSCaey/+P5Qg2qL51uEdsgnuYGMF4wMpz0/5VXw1FkmvMpNIxHXWrgA= X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2017 00:21:16.8472 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR07MB3422 Hi, This patch adds Decimal floating point support to aarch64. It is the base support in that since there is no hardware support for DFP, it just defines the ABI. The ABI I chose is that _Decimal32 is treated like float, _Decimal64 is treated like double and _Decimal128 is treated like long double. In that they are passed via the floating registers (sN, dN, qN). Is this ok an ABI? Is the patch ok? Bootstrapped and tested on aarch64-linux-gnu with --enable-decimal-float with no regressions and all of the dfp testcases pass. Thanks, Andrew Pinski gcc/ChangeLog: * config/aarch64/aarch64.c (aarch64_split_128bit_move): Handle TDmode. (aarch64_classify_address): Likewise. (aarch64_legitimize_address_displacement): Likewise. (aarch64_legitimize_address): Likewise. (aarch64_constant_pool_reload_icode): Handle SD, DD, and TD modes. (aarch64_secondary_reload): Handle TDmode. (aarch64_valid_floating_const): For decimal floating point return false. (aarch64_gimplify_va_arg_expr): Handle SD, DD, and TD modes. (aapcs_vfp_sub_candidate): Likewise. (aarch64_vfp_is_call_or_return_candidate): Handle MODE_DECIMAL_FLOAT. (aarch64_scalar_mode_supported_p): For DECIMAL_FLOAT_MODE_P, return default_decimal_float_supported_p. * config/aarch64/iterators.md (GPF_TF_F16): Add SD, DD, and TD modes. (SFD): New iterator. (DFD): New iterator. (TFD): New iterator. (GPF_TF): Add SD, DD, and TD modes. (TX): Add TD mode. * config/aarch64/aarch64.md (*movsf_aarch64): Use SFD iterator. (*movdf_aarch64): Use DFD iterator. (*movtf_aarch64): Use TFD iterator. (define_split for TF): Use TFD iterator. gcc/testsuite/ChangeLog: * c-c++-common/dfp/pr39986.c: Allow for word instead of just long. libgcc/ChangeLog: * config.host (aarch64*-*-elf): Add t-dfprules to tmake_file. (aarch64*-*-freebsd*): Likewise. (aarch64*-*-linux*): Likewise. Index: config/aarch64/aarch64.c =================================================================== --- config/aarch64/aarch64.c (revision 250186) +++ config/aarch64/aarch64.c (working copy) @@ -1653,7 +1653,7 @@ aarch64_split_128bit_move (rtx dst, rtx machine_mode mode = GET_MODE (dst); - gcc_assert (mode == TImode || mode == TFmode); + gcc_assert (mode == TImode || mode == TFmode || mode == TDmode); gcc_assert (!(side_effects_p (src) || side_effects_p (dst))); gcc_assert (mode == GET_MODE (src) || GET_MODE (src) == VOIDmode); @@ -1673,11 +1673,16 @@ aarch64_split_128bit_move (rtx dst, rtx emit_insn (gen_aarch64_movtilow_di (dst, src_lo)); emit_insn (gen_aarch64_movtihigh_di (dst, src_hi)); } - else + else if (mode == TFmode) { emit_insn (gen_aarch64_movtflow_di (dst, src_lo)); emit_insn (gen_aarch64_movtfhigh_di (dst, src_hi)); } + else + { + emit_insn (gen_aarch64_movtdlow_di (dst, src_lo)); + emit_insn (gen_aarch64_movtdhigh_di (dst, src_hi)); + } return; } else if (GP_REGNUM_P (dst_regno) && FP_REGNUM_P (src_regno)) @@ -1690,11 +1695,16 @@ aarch64_split_128bit_move (rtx dst, rtx emit_insn (gen_aarch64_movdi_tilow (dst_lo, src)); emit_insn (gen_aarch64_movdi_tihigh (dst_hi, src)); } - else + else if (mode == TFmode) { emit_insn (gen_aarch64_movdi_tflow (dst_lo, src)); emit_insn (gen_aarch64_movdi_tfhigh (dst_hi, src)); } + else if (mode == TDmode) + { + emit_insn (gen_aarch64_movdi_tdlow (dst_lo, src)); + emit_insn (gen_aarch64_movdi_tdhigh (dst_hi, src)); + } return; } } @@ -4420,10 +4430,11 @@ aarch64_classify_address (struct aarch64 rtx op0, op1; /* On BE, we use load/store pair for all large int mode load/stores. - TI/TFmode may also use a load/store pair. */ + TI/TF/TDmode may also use a load/store pair. */ bool load_store_pair_p = (outer_code == PARALLEL || mode == TImode || mode == TFmode + || mode == TDmode || (BYTES_BIG_ENDIAN && aarch64_vect_struct_mode_p (mode))); @@ -4473,7 +4484,7 @@ aarch64_classify_address (struct aarch64 info->base = op0; info->offset = op1; - /* TImode and TFmode values are allowed in both pairs of X + /* TImode and TFmode and TDmode values are allowed in both pairs of X registers and individual Q registers. The available address modes are: X,X: 7-bit signed scaled offset @@ -4482,7 +4493,7 @@ aarch64_classify_address (struct aarch64 When performing the check for pairs of X registers i.e. LDP/STP pass down DImode since that is the natural size of the LDP/STP instruction memory accesses. */ - if (mode == TImode || mode == TFmode) + if (mode == TImode || mode == TFmode || mode == TDmode) return (aarch64_offset_7bit_signed_scaled_p (DImode, offset) && (offset_9bit_signed_unscaled_p (mode, offset) || offset_12bit_unsigned_scaled_p (mode, offset))); @@ -4558,14 +4569,14 @@ aarch64_classify_address (struct aarch64 info->offset = XEXP (XEXP (x, 1), 1); offset = INTVAL (info->offset); - /* TImode and TFmode values are allowed in both pairs of X + /* TImode and TFmode and TDmode values are allowed in both pairs of X registers and individual Q registers. The available address modes are: X,X: 7-bit signed scaled offset Q: 9-bit signed offset We conservatively require an offset representable in either mode. */ - if (mode == TImode || mode == TFmode) + if (mode == TImode || mode == TFmode || mode == TDmode) return (aarch64_offset_7bit_signed_scaled_p (mode, offset) && offset_9bit_signed_unscaled_p (mode, offset)); @@ -4714,7 +4725,7 @@ aarch64_legitimize_address_displacement HOST_WIDE_INT offset = INTVAL (*disp); HOST_WIDE_INT base = offset & ~(GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3ffc); - if (mode == TImode || mode == TFmode + if (mode == TImode || mode == TFmode || mode == TDmode || (offset & (GET_MODE_SIZE (mode) - 1)) != 0) base = (offset + 0x100) & ~0x1ff; @@ -5649,7 +5660,7 @@ aarch64_legitimize_address (rtx x, rtx / /* Small negative offsets are supported. */ else if (IN_RANGE (offset, -256, 0)) base_offset = 0; - else if (mode == TImode || mode == TFmode) + else if (mode == TImode || mode == TFmode || mode == TDmode) base_offset = (offset + 0x100) & ~0x1ff; /* Use 12-bit offset by access size. */ else @@ -5681,6 +5692,15 @@ aarch64_constant_pool_reload_icode (mach case TFmode: return CODE_FOR_aarch64_reload_movcptfdi; + case SDmode: + return CODE_FOR_aarch64_reload_movcpsddi; + + case DDmode: + return CODE_FOR_aarch64_reload_movcpdddi; + + case TDmode: + return CODE_FOR_aarch64_reload_movcptddi; + case V8QImode: return CODE_FOR_aarch64_reload_movcpv8qidi; @@ -5731,25 +5751,27 @@ aarch64_secondary_reload (bool in_p ATTR /* Without the TARGET_SIMD instructions we cannot move a Q register to a Q register directly. We need a scratch. */ - if (REG_P (x) && (mode == TFmode || mode == TImode) && mode == GET_MODE (x) + if (REG_P (x) && (mode == TFmode || mode == TDmode || mode == TImode) && mode == GET_MODE (x) && FP_REGNUM_P (REGNO (x)) && !TARGET_SIMD && reg_class_subset_p (rclass, FP_REGS)) { if (mode == TFmode) sri->icode = CODE_FOR_aarch64_reload_movtf; + else if (mode == TDmode) + sri->icode = CODE_FOR_aarch64_reload_movtd; else if (mode == TImode) sri->icode = CODE_FOR_aarch64_reload_movti; return NO_REGS; } - /* A TFmode or TImode memory access should be handled via an FP_REGS + /* A TFmode or TImode or TDmode memory access should be handled via an FP_REGS because AArch64 has richer addressing modes for LDR/STR instructions than LDP/STP instructions. */ if (TARGET_FLOAT && rclass == GENERAL_REGS && GET_MODE_SIZE (mode) == 16 && MEM_P (x)) return FP_REGS; - if (rclass == FP_REGS && (mode == TImode || mode == TFmode) && CONSTANT_P(x)) + if (rclass == FP_REGS && (mode == TImode || mode == TFmode || mode == TDmode) && CONSTANT_P(x)) return GENERAL_REGS; return NO_REGS; @@ -10215,6 +10237,10 @@ aarch64_legitimate_pic_operand_p (rtx x) static bool aarch64_valid_floating_const (machine_mode mode, rtx x) { + /* FIXME: Handle decimal floating point constants. */ + if (GET_MODE_CLASS (mode) == MODE_DECIMAL_FLOAT) + return false; + if (!CONST_DOUBLE_P (x)) return false; @@ -10636,6 +10662,18 @@ aarch64_gimplify_va_arg_expr (tree valis field_t = long_double_type_node; field_ptr_t = long_double_ptr_type_node; break; + case SDmode: + field_t = dfloat32_type_node; + field_ptr_t = dfloat32_ptr_type_node; + break; + case DDmode: + field_t = dfloat64_type_node; + field_ptr_t = dfloat64_ptr_type_node; + break; + case TDmode: + field_t = dfloat128_type_node; + field_ptr_t = dfloat128_ptr_type_node; + break; case HFmode: field_t = aarch64_fp16_type_node; field_ptr_t = aarch64_fp16_ptr_type_node; @@ -10802,7 +10840,9 @@ aapcs_vfp_sub_candidate (const_tree type case REAL_TYPE: mode = TYPE_MODE (type); if (mode != DFmode && mode != SFmode - && mode != TFmode && mode != HFmode) + && mode != TFmode && mode != HFmode + && mode != DDmode && mode != SDmode + && mode != TDmode) return -1; if (*modep == VOIDmode) @@ -11030,7 +11070,9 @@ aarch64_vfp_is_call_or_return_candidate if (is_ha != NULL) *is_ha = false; - if ((!composite_p && GET_MODE_CLASS (mode) == MODE_FLOAT) + if ((!composite_p + && (GET_MODE_CLASS (mode) == MODE_FLOAT + || GET_MODE_CLASS (mode) == MODE_DECIMAL_FLOAT)) || aarch64_short_vector_p (type, mode)) { *count = 1; @@ -15028,6 +15070,9 @@ aarch64_libgcc_floating_mode_supported_p static bool aarch64_scalar_mode_supported_p (machine_mode mode) { + if (DECIMAL_FLOAT_MODE_P (mode)) + return default_decimal_float_supported_p (); + return (mode == HFmode ? true : default_scalar_mode_supported_p (mode)); Index: config/aarch64/aarch64.md =================================================================== --- config/aarch64/aarch64.md (revision 250186) +++ config/aarch64/aarch64.md (working copy) @@ -1081,11 +1081,11 @@ (define_insn "*movhf_aarch64" (set_attr "simd" "yes,yes,yes,yes,*,*,*,*,*")] ) -(define_insn "*movsf_aarch64" - [(set (match_operand:SF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r") - (match_operand:SF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))] - "TARGET_FLOAT && (register_operand (operands[0], SFmode) - || aarch64_reg_or_fp_zero (operands[1], SFmode))" +(define_insn "*mov_aarch64" + [(set (match_operand:SFD 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r") + (match_operand:SFD 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))] + "TARGET_FLOAT && (register_operand (operands[0], mode) + || aarch64_reg_or_fp_zero (operands[1], mode))" "@ movi\\t%0.2s, #0 fmov\\t%s0, %w1 @@ -1102,11 +1102,11 @@ (define_insn "*movsf_aarch64" (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")] ) -(define_insn "*movdf_aarch64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r") - (match_operand:DF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))] - "TARGET_FLOAT && (register_operand (operands[0], DFmode) - || aarch64_reg_or_fp_zero (operands[1], DFmode))" +(define_insn "*mov_aarch64" + [(set (match_operand:DFD 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r") + (match_operand:DFD 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))] + "TARGET_FLOAT && (register_operand (operands[0], mode) + || aarch64_reg_or_fp_zero (operands[1], mode))" "@ movi\\t%d0, #0 fmov\\t%d0, %x1 @@ -1123,13 +1123,13 @@ (define_insn "*movdf_aarch64" (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")] ) -(define_insn "*movtf_aarch64" - [(set (match_operand:TF 0 +(define_insn "*mov_aarch64" + [(set (match_operand:TFD 0 "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r,m ,m") - (match_operand:TF 1 + (match_operand:TFD 1 "general_operand" " w,?r, ?r,w ,Y,Y ,m,w,m ,?r,Y"))] - "TARGET_FLOAT && (register_operand (operands[0], TFmode) - || aarch64_reg_or_fp_zero (operands[1], TFmode))" + "TARGET_FLOAT && (register_operand (operands[0], mode) + || aarch64_reg_or_fp_zero (operands[1], mode))" "@ mov\\t%0.16b, %1.16b # @@ -1149,8 +1149,8 @@ (define_insn "*movtf_aarch64" ) (define_split - [(set (match_operand:TF 0 "register_operand" "") - (match_operand:TF 1 "aarch64_reg_or_imm" ""))] + [(set (match_operand:TFD 0 "register_operand" "") + (match_operand:TFD 1 "aarch64_reg_or_imm" ""))] "reload_completed && aarch64_split_128bit_move_p (operands[0], operands[1])" [(const_int 0)] { Index: config/aarch64/iterators.md =================================================================== --- config/aarch64/iterators.md (revision 250186) +++ config/aarch64/iterators.md (working copy) @@ -44,14 +44,23 @@ (define_mode_iterator GPF [SF DF]) ;; Iterator for all scalar floating point modes (HF, SF, DF) (define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF]) -;; Iterator for all scalar floating point modes (HF, SF, DF and TF) -(define_mode_iterator GPF_TF_F16 [HF SF DF TF]) +;; Iterator for all scalar floating point modes (HF, SF, DF and TF [SD, DD, and TD]) +(define_mode_iterator GPF_TF_F16 [HF SF DF TF SD DD TD]) + +;; Iterator for scalar 32bit fp modes (SF, SD) +(define_mode_iterator SFD [SD SF]) + +;; Iterator for scalar 64bit fp modes (DF, DD) +(define_mode_iterator DFD [DD DF]) + +;; Iterator for scalar 128bit fp modes (TF, TD) +(define_mode_iterator TFD [TD TF]) ;; Double vector modes. (define_mode_iterator VDF [V2SF V4HF]) -;; Iterator for all scalar floating point modes (SF, DF and TF) -(define_mode_iterator GPF_TF [SF DF TF]) +;; Iterator for all scalar floating point modes (SF, DF and TF [SD, DD, and TD]) +(define_mode_iterator GPF_TF [SF DF TF SD DD TD]) ;; Integer vector modes. (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) @@ -224,7 +233,7 @@ (define_mode_iterator VB [V8QI V16QI]) ;; 2 and 4 lane SI modes. (define_mode_iterator VS [V2SI V4SI]) -(define_mode_iterator TX [TI TF]) +(define_mode_iterator TX [TI TF TD]) ;; Opaque structure modes. (define_mode_iterator VSTRUCT [OI CI XI]) Index: testsuite/c-c++-common/dfp/pr39986.c =================================================================== --- testsuite/c-c++-common/dfp/pr39986.c (revision 250186) +++ testsuite/c-c++-common/dfp/pr39986.c (working copy) @@ -14,19 +14,19 @@ _Decimal128 f = -678901.234e-6dl; /* The first value is DPD, the second is BID. The order differs depending on whether the target is big-endian or little-endian. */ -/* { dg-final { scan-assembler ".long\t(572653859|822183807)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(572653859|822183807)\n" } } */ -/* { dg-final { scan-assembler ".long\t(-1572863965|-1308622825)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(-1572863965|-1308622825)\n" } } */ -/* { dg-final { scan-assembler ".long\t(52|34)\n" } } */ -/* { dg-final { scan-assembler ".long\t(572784640|824180736)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(52|34)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(572784640|824180736)\n" } } */ -/* { dg-final { scan-assembler ".long\t(4736|4500)\n" } } */ -/* { dg-final { scan-assembler ".long\t(-1574174720|-1319108608)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(4736|4500)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(-1574174720|-1319108608)\n" } } */ -/* { dg-final { scan-assembler ".long\t(-1975952433|957645077)\n" } } */ -/* { dg-final { scan-assembler ".long\t(190215|132222)\n" } } */ -/* { dg-final { scan-assembler ".long\t(574193664|835452928)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(-1975952433|957645077)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(190215|132222)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(574193664|835452928)\n" } } */ -/* { dg-final { scan-assembler ".long\t(931280180|678901234)\n" } } */ -/* { dg-final { scan-assembler ".long\t(-1576681472|-1339162624)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(931280180|678901234)\n" } } */ +/* { dg-final { scan-assembler ".(word|long)\t(-1576681472|-1339162624)\n" } } */