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Alder Lake Intel Hybrid Technology is based on Tremont and plus ADCX/AVX/AVX2/BMI/BMI2/F16C/FMA/LZCNT/ PCONFIG/PKU/VAES/VPCLMULQDQ/SERIALIZE/HRESET/KL/WIDEKL/AVX-VNNI For detailed information, please refer to https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Bootstrap is ok, and no regressions for i386/x86-64 testsuite. OK for master backport to GCC 10? [PATCH] Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2 Alder Lake Intel Hybrid Technology will not support Intel(r) AVX-512. ISA features such as Intel(r) AVX, AVX-VNNI, Intel(r) AVX2, and UMONITOR/UMWAIT/TPAUSE are supported. gcc/ * config/i386/i386.h (PTA_ALDERLAKE): Change alderlake ISA list. * config/i386/i386-options.c (m_CORE_AVX2): Add m_ALDERLAKE. *common/config/i386/cpuinfo.h: (get_intel_cpu): Add rocketlake model. * doc/invoke.texi: Change alderlake ISA list. --- gcc/common/config/i386/cpuinfo.h | 1 + gcc/config/i386/i386-options.c | 2 +- gcc/config/i386/i386.h | 7 ++++--- gcc/doc/invoke.texi | 9 +++++---- 4 files changed, 11 insertions(+), 8 deletions(-) Thanks, Lili. diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index dbce022620a..c1ee7a1f8b8 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -476,6 +476,7 @@ get_intel_cpu (struct __processor_model *cpu_model, cpu_model->__cpu_subtype = INTEL_COREI7_TIGERLAKE; break; case 0x97: + case 0x9a: /* Alder Lake. */ cpu = "alderlake"; CHECK___builtin_cpu_is ("corei7"); diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index a8d06735d79..02e9c97d174 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -129,7 +129,7 @@ along with GCC; see the file COPYING3. If not see #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \ | m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE \ | m_TIGERLAKE | m_COOPERLAKE | m_SAPPHIRERAPIDS) -#define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512) +#define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_ALDERLAKE | m_CORE_AVX512) #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2) #define m_GOLDMONT (HOST_WIDE_INT_1U<