From patchwork Wed May 25 17:19:03 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 97384 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 445C0B6F94 for ; Thu, 26 May 2011 03:19:39 +1000 (EST) Received: (qmail 22061 invoked by alias); 25 May 2011 17:19:35 -0000 Received: (qmail 22050 invoked by uid 22791); 25 May 2011 17:19:33 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RFC_ABUSE_POST X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 25 May 2011 17:19:04 +0000 Received: by qwh5 with SMTP id 5so4493716qwh.20 for ; Wed, 25 May 2011 10:19:03 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.24.138 with SMTP id v10mr1910342qcb.39.1306343943322; Wed, 25 May 2011 10:19:03 -0700 (PDT) Received: by 10.229.11.143 with HTTP; Wed, 25 May 2011 10:19:03 -0700 (PDT) In-Reply-To: <4DDD31C2.2010607@redhat.com> References: <4DDCD96B.90402@redhat.com> <4DDD13E3.6070103@redhat.com> <4DDD1835.50007@redhat.com> <4DDD1BB8.4080307@redhat.com> <4DDD31C2.2010607@redhat.com> Date: Wed, 25 May 2011 10:19:03 -0700 Message-ID: Subject: Re: PATCH: Add pause intrinsic From: "H.J. Lu" To: Andrew Haley Cc: gcc-patches@gcc.gnu.org X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Wed, May 25, 2011 at 9:43 AM, Andrew Haley wrote: > On 05/25/2011 04:32 PM, H.J. Lu wrote: >> On Wed, May 25, 2011 at 8:27 AM, Richard Guenther >> wrote: >>> On Wed, May 25, 2011 at 5:20 PM, Michael Matz wrote: >>>> Hi, >>>> >>>> On Wed, 25 May 2011, Richard Guenther wrote: >>>> >>>>>>> asm volatile ("" : : : "memory") in fact will work as a full memory >>>>>>> barrier >>>>>> >>>>>> How?  You surely need MFENCE or somesuch, unless all you care about is >>>>>> a compiler barrier.  That's what I think needs to be clarified. >>>>> >>>>> Well, yes, I'm talking about the compiler memory barrier. >>>> >>>> Something that we conventionally call "optimization barrier" :)  memory >>>> barrier has a fixed meaning which we shouldn't use in this case, it's >>>> confusing. >>> >>> Sure ;) >>> >>> And to keep the info in a suitable thread what I'd like to improve here >>> is to make us disambiguate memory loads/stores against asms that >>> have no memory outputs/inputs. >>> >> >> Please let me know how I should improve the document, > > "Compiler memory barrier" seems to be well-understood.  I suggest > > +Generates the @code{pause} machine instruction with a compiler memory barrier. > > It's clear enough. > > Andrew. > I checked in this. Thanks. Index: doc/extend.texi =================================================================== --- doc/extend.texi (revision 174216) +++ doc/extend.texi (working copy) @@ -8699,7 +8699,8 @@ The following built-in function is alway @table @code @item void __builtin_ia32_pause (void) -Generates the @code{pause} machine instruction with full memory barrier. +Generates the @code{pause} machine instruction with a compiler memory +barrier. @end table The following floating point built-in functions are made available in the Index: ChangeLog =================================================================== --- ChangeLog (revision 174216) +++ ChangeLog (working copy) @@ -1,3 +1,8 @@ +2011-05-25 H.J. Lu + + * doc/extend.texi (X86 Built-in Functions): Update pause + intrinsic. + 2011-05-25 Bernd Schmidt PR bootstrap/49160