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[AArch64] Enable CLI for Armv8.6-A f64mm

Message ID AM6PR08MB4326D7DEE11B949234434854E0350@AM6PR08MB4326.eurprd08.prod.outlook.com
State New
Headers show
Series [AArch64] Enable CLI for Armv8.6-A f64mm | expand

Commit Message

Matthew Malcomson Jan. 13, 2020, 11:33 a.m. UTC 
This patch is necessary for sve-ld1ro intrinsic I posted in
https://gcc.gnu.org/ml/gcc-patches/2020-01/msg00466.html .

I had mistakenly thought this option was already enabled upstream.

This provides the option +f64mm, that turns on the 64 bit floating point
matrix multiply extension.  This extension is only available for
AArch64.  Turning on this extension also turns on the SVE extension.

This extension is optional and only available at Armv8.2-A and onward.

We also add the ACLE defined macro for this extension.

Tested on aarch64 cross compiler from x86.

gcc/ChangeLog:

2020-01-13  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
	Introduce this ACLE specified predefined macro.
	* config/aarch64/aarch64-option-extensions.def (f64mm): New.
	(fp): Disabling this disables f64mm.
	(simd): Disabling this disables f64mm.
	(fp16): Disabling this disables f64mm.
	(sve): Disabling this disables f64mm.
	* config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
	(AARCH64_ISA_F64MM): New.
	(TARGET_F64MM): New.
	* doc/invoke.texi (f64mm): Document new option.

gcc/testsuite/ChangeLog:

2020-01-13  Matthew Malcomson  <matthew.malcomson@arm.com>

	* gcc.target/aarch64/pragma_cpp_predefs_2.c: Check for f64mm
	predef.



###############     Attachment also inlined for ease of reply    ###############
diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index 9ccca422b045fcd6875f192680220b2af9d59d31..22fc4a5e337acb4cdd96618b57736f55892bd0e7 100644
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -166,6 +166,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
   aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile);
 
   aarch64_def_or_undef (TARGET_I8MM, "__ARM_FEATURE_MATMUL_INT8", pfile);
+  aarch64_def_or_undef (TARGET_F64MM, "__ARM_FEATURE_MATMUL_FP64", pfile);
   aarch64_def_or_undef (TARGET_BF16_SIMD,
 			"__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile);
   aarch64_def_or_undef (TARGET_BF16_FP,
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index 5022a1b3552f35364e35b3955bf2c39a33ab0752..6057b33033a0f3a8be7d656dc1e459d4d93b2842 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -53,26 +53,26 @@
 /* Enabling "fp" just enables "fp".
    Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2",
    "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
-   "sve2-bitperm", "i8mm" and "bf16".  */
+   "sve2-bitperm", "i8mm", "f64mm", and "bf16".  */
 AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | \
 		      AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | \
 		      AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | \
 		      AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
 		      AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
 		      AARCH64_FL_SVE2_BITPERM | AARCH64_FL_I8MM | \
-		      AARCH64_FL_BF16, false, "fp")
+		      AARCH64_FL_F64MM | AARCH64_FL_BF16, false, "fp")
 
 /* Enabling "simd" also enables "fp".
    Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3",
    "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
-   "sve2-bitperm", and "i8mm".  */
+   "sve2-bitperm", "i8mm", and "f64mm".  */
 AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, \
 		      AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | \
 		      AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | \
 		      AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
 		      AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
 		      AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM | \
-		      AARCH64_FL_I8MM, false, \
+		      AARCH64_FL_I8MM | AARCH64_FL_F64MM, false, \
 		      "asimd")
 
 /* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2".
@@ -92,12 +92,13 @@ AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, false, "crc32")
 AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, false, "atomics")
 
 /* Enabling "fp16" also enables "fp".
-   Disabling "fp16" disables "fp16", "fp16fml", "sve", "sve2", "sve2-aes",
-   "sve2-sha3", "sve2-sm4", and "bitperm".  */
+   Disabling "fp16" disables "fp16", "fp16fml", "sve", "f64mm", "sve2",
+   "sve2-aes", "sve2-sha3", "sve2-sm4", and "bitperm".  */
 AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, \
-		      AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
-		      AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
-		      AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, \
+		      AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_F64MM | \
+		      AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
+		      AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
+		      AARCH64_FL_SVE2_BITPERM, false, \
 		      "fphp asimdhp")
 
 /* Enabling or disabling "rcpc" only changes "rcpc".  */
@@ -140,12 +141,13 @@ AARCH64_OPT_EXTENSION("fp16fml", AARCH64_FL_F16FML, \
 		      AARCH64_FL_FP | AARCH64_FL_F16, 0, false, "asimdfhm")
 
 /* Enabling "sve" also enables "fp16", "fp" and "simd".
-   Disabling "sve" disables "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4"
-   and "sve2-bitperm".  */
+   Disabling "sve" disables "sve", "f64mm", "sve2", "sve2-aes", "sve2-sha3",
+   "sve2-sm4" and "sve2-bitperm".  */
 AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | \
-		      AARCH64_FL_F16, AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
-		      AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
-		      AARCH64_FL_SVE2_BITPERM, false, "sve")
+		      AARCH64_FL_F16, AARCH64_FL_F64MM | AARCH64_FL_SVE2 | \
+		      AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
+		      AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, \
+		      false, "sve")
 
 /* Enabling/Disabling "profile" does not enable/disable any other feature.  */
 AARCH64_OPT_EXTENSION("profile", AARCH64_FL_PROFILE, 0, 0, false, "")
@@ -205,6 +207,12 @@ AARCH64_OPT_EXTENSION("tme", AARCH64_FL_TME, 0, 0, false, "")
 AARCH64_OPT_EXTENSION("i8mm", AARCH64_FL_I8MM, \
 		      AARCH64_FL_SIMD | AARCH64_FL_FP, 0, false, "i8mm")
 
+/* Enabling "f64mm" also enables "sve", "fp16", "fp", and "simd".
+   Disabling "f64mm" only disables "f64mm".  */
+AARCH64_OPT_EXTENSION("f64mm", AARCH64_FL_F64MM, \
+		      AARCH64_FL_SVE | AARCH64_FL_F16 | AARCH64_FL_FP | \
+		      AARCH64_FL_SIMD, 0, false, "f64mm")
+
 /* Enabling "bf16" also enables "simd" and "fp".
    Disabling "bf16" only disables "bf16".  */
 AARCH64_OPT_EXTENSION("bf16", AARCH64_FL_BF16, \
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 04dabd46437cf650e38e085d219c4e629b537e67..31d0f7d8466325d34d5584a911db0547c8297fa1 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -211,6 +211,9 @@ extern unsigned aarch64_architecture_version;
 /* Brain half-precision floating-point (BFloat16) Extension.  */
 #define AARCH64_FL_BF16	      (1ULL << 36)
 
+/* 8-bit Integer Matrix Multiply (F64MM) extensions.  */
+#define AARCH64_FL_F64MM      (1ULL << 37)
+
 /* Has FP and SIMD.  */
 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
 
@@ -263,6 +266,7 @@ extern unsigned aarch64_architecture_version;
 #define AARCH64_ISA_MEMTAG	   (aarch64_isa_flags & AARCH64_FL_MEMTAG)
 #define AARCH64_ISA_V8_6	   (aarch64_isa_flags & AARCH64_FL_V8_6)
 #define AARCH64_ISA_I8MM	   (aarch64_isa_flags & AARCH64_FL_I8MM)
+#define AARCH64_ISA_F64MM	   (aarch64_isa_flags & AARCH64_FL_F64MM)
 #define AARCH64_ISA_BF16	   (aarch64_isa_flags & AARCH64_FL_BF16)
 
 /* Crypto is an optional extension to AdvSIMD.  */
@@ -326,6 +330,9 @@ extern unsigned aarch64_architecture_version;
 /* I8MM instructions are enabled through +i8mm.  */
 #define TARGET_I8MM (AARCH64_ISA_I8MM)
 
+/* F64MM instructions are enabled through +f64mm.  */
+#define TARGET_F64MM (AARCH64_ISA_F64MM)
+
 /* BF16 instructions are enabled through +bf16.  */
 #define TARGET_BF16_FP (AARCH64_ISA_BF16)
 #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 53df4b1fdf9884d0b7cb73341d717887e79fef9c..47668731efc25dbf32a3b6b38817d7762bbfa93f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -16130,7 +16130,7 @@ and the features that they enable by default:
 @item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a}
 @item @samp{armv8.4-a} @tab Armv8.4-A @tab @samp{armv8.3-a}, @samp{+fp16fml}, @samp{+dotprod}
 @item @samp{armv8.5-a} @tab Armv8.5-A @tab @samp{armv8.4-a}, @samp{+sb}, @samp{+ssbs}, @samp{+predres}
-@item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}
+@item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}, @samp{+f64mm}
 @end multitable
 
 The value @samp{native} is available on native AArch64 GNU/Linux and
@@ -16365,6 +16365,10 @@ Enable 8-bit Integer Matrix Multiply instructions.  This also enables
 Advanced SIMD and floating-point instructions.  This option is enabled by
 default for @option{-march=armv8.6-a}.  Use of this option with architectures
 prior to Armv8.2-A is not supported.
+@item f64mm
+Enable 64-bit Floating point Matrix Multiply instructions.  This also enables
+SVE instructions.  Use of this option with architectures prior to Armv8.2-A is
+not supported.
 @item bf16
 Enable brain half-precision floating-point instructions.  This also enables
 Advanced SIMD and floating-point instructions.  This option is enabled by
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
index f61d635bd2abc9fd8ddfb6dc77933de45ca833ee..27d475f3cc0dc9debd4e58f010bb54f44f6ca5b6 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
@@ -22,11 +22,18 @@
 #error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"
 #endif
 
+#ifdef __ARM_FEATURE_MATMUL_FP64
+#error "__ARM_FEATURE_MATMUL_FP64 is defined but should not be!"
+#endif
+
 #pragma GCC push_options
 #pragma GCC target ("arch=armv8.6-a")
 #ifndef __ARM_FEATURE_MATMUL_INT8
 #error "__ARM_FEATURE_MATMUL_INT8 is not defined but should be!"
 #endif
+#ifdef __ARM_FEATURE_MATMUL_FP64
+#error "__ARM_FEATURE_MATMUL_FP64 is defined but should not be!"
+#endif
 #pragma GCC pop_options
 
 #pragma GCC push_options
@@ -37,6 +44,13 @@
 #pragma GCC pop_options
 
 #pragma GCC push_options
+#pragma GCC target ("arch=armv8.2-a+f64mm")
+#ifndef __ARM_FEATURE_MATMUL_FP64
+#error "__ARM_FEATURE_MATMUL_FP64 is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
 #pragma GCC target ("arch=armv8.6-a+nosimd")
 #ifdef __ARM_FEATURE_MATMUL_INT8
 #error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"

Comments

Richard Sandiford Jan. 16, 2020, 5:21 p.m. UTC | #1 
Matthew Malcomson <Matthew.Malcomson@arm.com> writes:
> This patch is necessary for sve-ld1ro intrinsic I posted in
> https://gcc.gnu.org/ml/gcc-patches/2020-01/msg00466.html .
>
> I had mistakenly thought this option was already enabled upstream.
>
> This provides the option +f64mm, that turns on the 64 bit floating point
> matrix multiply extension.  This extension is only available for
> AArch64.  Turning on this extension also turns on the SVE extension.
>
> This extension is optional and only available at Armv8.2-A and onward.
>
> We also add the ACLE defined macro for this extension.
>
> Tested on aarch64 cross compiler from x86.
>
> gcc/ChangeLog:
>
> 2020-01-13  Matthew Malcomson  <matthew.malcomson@arm.com>
>
> 	* config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
> 	Introduce this ACLE specified predefined macro.
> 	* config/aarch64/aarch64-option-extensions.def (f64mm): New.
> 	(fp): Disabling this disables f64mm.
> 	(simd): Disabling this disables f64mm.
> 	(fp16): Disabling this disables f64mm.
> 	(sve): Disabling this disables f64mm.
> 	* config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
> 	(AARCH64_ISA_F64MM): New.
> 	(TARGET_F64MM): New.
> 	* doc/invoke.texi (f64mm): Document new option.

Sorry for the slow reply, somehow missed this originally.

> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
> index 5022a1b3552f35364e35b3955bf2c39a33ab0752..6057b33033a0f3a8be7d656dc1e459d4d93b2842 100644
> --- a/gcc/config/aarch64/aarch64-option-extensions.def
> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
> @@ -53,26 +53,26 @@
>  /* Enabling "fp" just enables "fp".
>     Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2",
>     "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
> -   "sve2-bitperm", "i8mm" and "bf16".  */
> +   "sve2-bitperm", "i8mm", "f64mm", and "bf16".  */
>  AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | \
>  		      AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | \
>  		      AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | \
>  		      AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
>  		      AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
>  		      AARCH64_FL_SVE2_BITPERM | AARCH64_FL_I8MM | \
> -		      AARCH64_FL_BF16, false, "fp")
> +		      AARCH64_FL_F64MM | AARCH64_FL_BF16, false, "fp")
>  
>  /* Enabling "simd" also enables "fp".
>     Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3",
>     "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
> -   "sve2-bitperm", and "i8mm".  */
> +   "sve2-bitperm", "i8mm", and "f64mm".  */
>  AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, \
>  		      AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | \
>  		      AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | \
>  		      AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
>  		      AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
>  		      AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM | \
> -		      AARCH64_FL_I8MM, false, \
> +		      AARCH64_FL_I8MM | AARCH64_FL_F64MM, false, \
>  		      "asimd")
>  
>  /* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2".
> @@ -92,12 +92,13 @@ AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, false, "crc32")
>  AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, false, "atomics")
>  
>  /* Enabling "fp16" also enables "fp".
> -   Disabling "fp16" disables "fp16", "fp16fml", "sve", "sve2", "sve2-aes",
> -   "sve2-sha3", "sve2-sm4", and "bitperm".  */
> +   Disabling "fp16" disables "fp16", "fp16fml", "sve", "f64mm", "sve2",
> +   "sve2-aes", "sve2-sha3", "sve2-sm4", and "bitperm".  */
>  AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, \
> -		      AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
> -		      AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
> -		      AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, \
> +		      AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_F64MM | \
> +		      AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
> +		      AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
> +		      AARCH64_FL_SVE2_BITPERM, false, \
>  		      "fphp asimdhp")

Minor (of course), but it'd probably better to keep the order of the
options consistent.  Above "f64mm" came at the end, after "i8mm" and
the SVE options, so let's do the same here.  Could you fix
s/"bitperm"/"sve2-bitperm" while you're there?

> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 53df4b1fdf9884d0b7cb73341d717887e79fef9c..47668731efc25dbf32a3b6b38817d7762bbfa93f 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -16130,7 +16130,7 @@ and the features that they enable by default:
>  @item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a}
>  @item @samp{armv8.4-a} @tab Armv8.4-A @tab @samp{armv8.3-a}, @samp{+fp16fml}, @samp{+dotprod}
>  @item @samp{armv8.5-a} @tab Armv8.5-A @tab @samp{armv8.4-a}, @samp{+sb}, @samp{+ssbs}, @samp{+predres}
> -@item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}
> +@item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}, @samp{+f64mm}
>  @end multitable

The patch doesn't enable f64mm by default for Arm8.6-A.

OK without that hunk and with the change above, thanks.

Richard
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index 9ccca422b045fcd6875f192680220b2af9d59d31..22fc4a5e337acb4cdd96618b57736f55892bd0e7 100644
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -166,6 +166,7 @@  aarch64_update_cpp_builtins (cpp_reader *pfile)
   aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile);
 
   aarch64_def_or_undef (TARGET_I8MM, "__ARM_FEATURE_MATMUL_INT8", pfile);
+  aarch64_def_or_undef (TARGET_F64MM, "__ARM_FEATURE_MATMUL_FP64", pfile);
   aarch64_def_or_undef (TARGET_BF16_SIMD,
 			"__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile);
   aarch64_def_or_undef (TARGET_BF16_FP,
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index 5022a1b3552f35364e35b3955bf2c39a33ab0752..6057b33033a0f3a8be7d656dc1e459d4d93b2842 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -53,26 +53,26 @@ 
 /* Enabling "fp" just enables "fp".
    Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2",
    "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
-   "sve2-bitperm", "i8mm" and "bf16".  */
+   "sve2-bitperm", "i8mm", "f64mm", and "bf16".  */
 AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | \
 		      AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | \
 		      AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | \
 		      AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
 		      AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
 		      AARCH64_FL_SVE2_BITPERM | AARCH64_FL_I8MM | \
-		      AARCH64_FL_BF16, false, "fp")
+		      AARCH64_FL_F64MM | AARCH64_FL_BF16, false, "fp")
 
 /* Enabling "simd" also enables "fp".
    Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3",
    "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
-   "sve2-bitperm", and "i8mm".  */
+   "sve2-bitperm", "i8mm", and "f64mm".  */
 AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, \
 		      AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | \
 		      AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | \
 		      AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
 		      AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
 		      AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM | \
-		      AARCH64_FL_I8MM, false, \
+		      AARCH64_FL_I8MM | AARCH64_FL_F64MM, false, \
 		      "asimd")
 
 /* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2".
@@ -92,12 +92,13 @@  AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, false, "crc32")
 AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, false, "atomics")
 
 /* Enabling "fp16" also enables "fp".
-   Disabling "fp16" disables "fp16", "fp16fml", "sve", "sve2", "sve2-aes",
-   "sve2-sha3", "sve2-sm4", and "bitperm".  */
+   Disabling "fp16" disables "fp16", "fp16fml", "sve", "f64mm", "sve2",
+   "sve2-aes", "sve2-sha3", "sve2-sm4", and "bitperm".  */
 AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, \
-		      AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
-		      AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
-		      AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, \
+		      AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_F64MM | \
+		      AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
+		      AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
+		      AARCH64_FL_SVE2_BITPERM, false, \
 		      "fphp asimdhp")
 
 /* Enabling or disabling "rcpc" only changes "rcpc".  */
@@ -140,12 +141,13 @@  AARCH64_OPT_EXTENSION("fp16fml", AARCH64_FL_F16FML, \
 		      AARCH64_FL_FP | AARCH64_FL_F16, 0, false, "asimdfhm")
 
 /* Enabling "sve" also enables "fp16", "fp" and "simd".
-   Disabling "sve" disables "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4"
-   and "sve2-bitperm".  */
+   Disabling "sve" disables "sve", "f64mm", "sve2", "sve2-aes", "sve2-sha3",
+   "sve2-sm4" and "sve2-bitperm".  */
 AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | \
-		      AARCH64_FL_F16, AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
-		      AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
-		      AARCH64_FL_SVE2_BITPERM, false, "sve")
+		      AARCH64_FL_F16, AARCH64_FL_F64MM | AARCH64_FL_SVE2 | \
+		      AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
+		      AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, \
+		      false, "sve")
 
 /* Enabling/Disabling "profile" does not enable/disable any other feature.  */
 AARCH64_OPT_EXTENSION("profile", AARCH64_FL_PROFILE, 0, 0, false, "")
@@ -205,6 +207,12 @@  AARCH64_OPT_EXTENSION("tme", AARCH64_FL_TME, 0, 0, false, "")
 AARCH64_OPT_EXTENSION("i8mm", AARCH64_FL_I8MM, \
 		      AARCH64_FL_SIMD | AARCH64_FL_FP, 0, false, "i8mm")
 
+/* Enabling "f64mm" also enables "sve", "fp16", "fp", and "simd".
+   Disabling "f64mm" only disables "f64mm".  */
+AARCH64_OPT_EXTENSION("f64mm", AARCH64_FL_F64MM, \
+		      AARCH64_FL_SVE | AARCH64_FL_F16 | AARCH64_FL_FP | \
+		      AARCH64_FL_SIMD, 0, false, "f64mm")
+
 /* Enabling "bf16" also enables "simd" and "fp".
    Disabling "bf16" only disables "bf16".  */
 AARCH64_OPT_EXTENSION("bf16", AARCH64_FL_BF16, \
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 04dabd46437cf650e38e085d219c4e629b537e67..31d0f7d8466325d34d5584a911db0547c8297fa1 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -211,6 +211,9 @@  extern unsigned aarch64_architecture_version;
 /* Brain half-precision floating-point (BFloat16) Extension.  */
 #define AARCH64_FL_BF16	      (1ULL << 36)
 
+/* 8-bit Integer Matrix Multiply (F64MM) extensions.  */
+#define AARCH64_FL_F64MM      (1ULL << 37)
+
 /* Has FP and SIMD.  */
 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
 
@@ -263,6 +266,7 @@  extern unsigned aarch64_architecture_version;
 #define AARCH64_ISA_MEMTAG	   (aarch64_isa_flags & AARCH64_FL_MEMTAG)
 #define AARCH64_ISA_V8_6	   (aarch64_isa_flags & AARCH64_FL_V8_6)
 #define AARCH64_ISA_I8MM	   (aarch64_isa_flags & AARCH64_FL_I8MM)
+#define AARCH64_ISA_F64MM	   (aarch64_isa_flags & AARCH64_FL_F64MM)
 #define AARCH64_ISA_BF16	   (aarch64_isa_flags & AARCH64_FL_BF16)
 
 /* Crypto is an optional extension to AdvSIMD.  */
@@ -326,6 +330,9 @@  extern unsigned aarch64_architecture_version;
 /* I8MM instructions are enabled through +i8mm.  */
 #define TARGET_I8MM (AARCH64_ISA_I8MM)
 
+/* F64MM instructions are enabled through +f64mm.  */
+#define TARGET_F64MM (AARCH64_ISA_F64MM)
+
 /* BF16 instructions are enabled through +bf16.  */
 #define TARGET_BF16_FP (AARCH64_ISA_BF16)
 #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 53df4b1fdf9884d0b7cb73341d717887e79fef9c..47668731efc25dbf32a3b6b38817d7762bbfa93f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -16130,7 +16130,7 @@  and the features that they enable by default:
 @item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a}
 @item @samp{armv8.4-a} @tab Armv8.4-A @tab @samp{armv8.3-a}, @samp{+fp16fml}, @samp{+dotprod}
 @item @samp{armv8.5-a} @tab Armv8.5-A @tab @samp{armv8.4-a}, @samp{+sb}, @samp{+ssbs}, @samp{+predres}
-@item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}
+@item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}, @samp{+f64mm}
 @end multitable
 
 The value @samp{native} is available on native AArch64 GNU/Linux and
@@ -16365,6 +16365,10 @@  Enable 8-bit Integer Matrix Multiply instructions.  This also enables
 Advanced SIMD and floating-point instructions.  This option is enabled by
 default for @option{-march=armv8.6-a}.  Use of this option with architectures
 prior to Armv8.2-A is not supported.
+@item f64mm
+Enable 64-bit Floating point Matrix Multiply instructions.  This also enables
+SVE instructions.  Use of this option with architectures prior to Armv8.2-A is
+not supported.
 @item bf16
 Enable brain half-precision floating-point instructions.  This also enables
 Advanced SIMD and floating-point instructions.  This option is enabled by
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
index f61d635bd2abc9fd8ddfb6dc77933de45ca833ee..27d475f3cc0dc9debd4e58f010bb54f44f6ca5b6 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
@@ -22,11 +22,18 @@ 
 #error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"
 #endif
 
+#ifdef __ARM_FEATURE_MATMUL_FP64
+#error "__ARM_FEATURE_MATMUL_FP64 is defined but should not be!"
+#endif
+
 #pragma GCC push_options
 #pragma GCC target ("arch=armv8.6-a")
 #ifndef __ARM_FEATURE_MATMUL_INT8
 #error "__ARM_FEATURE_MATMUL_INT8 is not defined but should be!"
 #endif
+#ifdef __ARM_FEATURE_MATMUL_FP64
+#error "__ARM_FEATURE_MATMUL_FP64 is defined but should not be!"
+#endif
 #pragma GCC pop_options
 
 #pragma GCC push_options
@@ -37,6 +44,13 @@ 
 #pragma GCC pop_options
 
 #pragma GCC push_options
+#pragma GCC target ("arch=armv8.2-a+f64mm")
+#ifndef __ARM_FEATURE_MATMUL_FP64
+#error "__ARM_FEATURE_MATMUL_FP64 is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
 #pragma GCC target ("arch=armv8.6-a+nosimd")
 #ifdef __ARM_FEATURE_MATMUL_INT8
 #error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"