From patchwork Wed Nov 2 16:50:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 690481 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t8Dcx3MnWz9vDY for ; Thu, 3 Nov 2016 03:50:57 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=lcDCY18m; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:content-transfer-encoding:mime-version; q=dns; s= default; b=Z6Zxx5wQ9r7IPWTd+TBn8NtNATrKyw+HkUxetD3xjXGuc4iux9RCb ZDt0qmCfiNjjNGCe7wPZ5nHU89oADWsXVvVyEiKKneOoJbotDmpE9s3hehlnjjMF i24UoAt1LUzTGPHSMTiuxLNti6M5DWzNKswMjH4V7DE5f1g8VTOAI8= DKIM-Signature: v=1; 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Wed, 02 Nov 2016 16:50:37 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com (10.175.46.18) by VI1PR0801MB2094.eurprd08.prod.outlook.com (10.173.75.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.679.12; Wed, 2 Nov 2016 16:50:34 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) by AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) with mapi id 15.01.0693.009; Wed, 2 Nov 2016 16:50:34 +0000 From: Wilco Dijkstra To: GCC Patches , James Greenhalgh CC: nd Subject: Re: [PATCH][AArch64] Improve SHA1 scheduling Date: Wed, 2 Nov 2016 16:50:34 +0000 Message-ID: References: In-Reply-To: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-office365-filtering-correlation-id: eb3fa5d4-018b-4373-da40-08d403405d54 x-microsoft-exchange-diagnostics: 1; VI1PR0801MB2094; 7:ceou88dxLaN9EHzY4LUJ0vwdSfB1BqagyegsLXwoBWXkFJwxn5kI68bjtYI1fnhR8kwMCdTIXcbJ8BHfRzNFWfWRc4IwLY6LG2ecSEY5e4Ttxv8+lHiaNaiCqP30Zgd2w0ropFa/fNlMeEeD3hEYYB2qaaZ1fV8logn1qKAUKSzqXu9T/82ClGg/34YLKaXCKdTbWGMHkCY/D07cBYroKwbKh+8z1+8LNjSsWUSWWSNaHU60YvZ4xCO+eqz3BNaNlR1sBbwinYGk05e8QRmDtsMUmrTONf0PhL3S6jNNFSJ4WAHl3qsi8x6RO6qGpTVXwrz2E/LOPitS/Iq6+vDL03rVmDBON8cUNrN/FLipMD4= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:VI1PR0801MB2094; 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SCL:1; SRVR:VI1PR0801MB2094; H:AM5PR0802MB2610.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Nov 2016 16:50:34.2643 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0801MB2094 ping From: Wilco Dijkstra Sent: 25 October 2016 18:08 To: GCC Patches Cc: nd Subject: [PATCH][AArch64] Improve SHA1 scheduling   SHA1H instructions may be scheduled after a SHA1C instruction that uses the same input register.  However SHA1C updates its input, so if SHA1H is scheduled after it, it requires an extra move. Increase the priority of SHA1H to ensure it gets scheduled earlier, avoiding the move. Is this something the generic scheduler could do automatically for instructions with RMW operands? Passes bootstrap & regress. OK for commit? ChangeLog: 2016-10-25  Wilco Dijkstra          * config/aarch64/aarch64.c (aarch64_sched_adjust_priority)         New function.         (TARGET_SCHED_ADJUST_PRIORITY): Define target hook. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 9b2f9cb19343828dc39e9950ebbefe941521942a..2b25bd1bdd6f4e7737f8e04c3b3684cdff6c4b80 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -13668,6 +13668,26 @@ aarch64_sched_fusion_priority (rtx_insn *insn, int max_pri,    return;  }   +/* Implement the TARGET_SCHED_ADJUST_PRIORITY hook. +   Adjust priority of sha1h instructions so they are scheduled before +   other SHA1 instructions.  */ + +static int +aarch64_sched_adjust_priority (rtx_insn *insn, int priority) +{ +  rtx x = PATTERN (insn); + +  if (GET_CODE (x) == SET) +    { +      x = SET_SRC (x); + +      if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SHA1H) +       return priority + 10; +    } + +  return priority; +} +  /* Given OPERANDS of consecutive load/store, check if we can merge     them into ldp/stp.  LOAD is true if they are load instructions.     MODE is the mode of memory operands.  */ @@ -14431,6 +14451,9 @@ aarch64_optab_supported_p (int op, machine_mode mode1, machine_mode,  #undef TARGET_CAN_USE_DOLOOP_P  #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost   +#undef TARGET_SCHED_ADJUST_PRIORITY +#define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority +  #undef TARGET_SCHED_MACRO_FUSION_P  #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p