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Thu, 21 Jan 2021 11:36:01 +0000 To: GCC Patches Subject: [AArch64] Remove backend support for widen-sub Thread-Topic: [AArch64] Remove backend support for widen-sub Thread-Index: AQHW7+jw1JzhxFnWhk6uxj1zz8UNew== Date: Thu, 21 Jan 2021 11:36:01 +0000 Message-ID: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: yes X-MS-TNEF-Correlator: Authentication-Results-Original: gcc.gnu.org; dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=none action=none header.from=arm.com; x-originating-ip: [217.140.99.251] x-ms-publictraffictype: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: e82badf2-04cd-49fc-4094-08d8be00c137 x-ms-traffictypediagnostic: AM6PR08MB5175:|VI1PR08MB2799: x-ms-exchange-transport-forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true nodisclaimer: true x-ms-oob-tlc-oobclassifiers: OLM:8273;OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: kt65O4EQyGUKYWDWIm45lkmhmboFccXte90SSfmqBO1jQQcydfGji9Y0KW0i3cNtAQxfSL6e3O8VP7FzjveXK4mzbkMKMpMA3jdhFYe4MYRKWkJXXILwyvuvyc7XxCxtDLafiFZxKUoStj3UzfXNyX1BB/RqLpZiFM+z5x70bu9X6ORZCICAfXUN/p3qpLdRrIcsSlhFDLbk37eZqwy+D8N3fW1nhxLowe4W/drZw/Ia3TJvo0w5XVNonhwa7OhKYxjfEehLNLNLdvxPAZeKdm6K3rOue5pg6EMwRYbnpCQuRHxSRV7vVL7nzJMsmxVvCXyy1LdxVxvDtdX10Lv0PIX8yOq4vRhnxHFrCI7bEb5MrTObC2J14dXHOze8axdJWy8k2oFN/p32qAgNbX/D8w== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; 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CAT:NONE; SFS:(4636009)(376002)(346002)(396003)(39860400002)(136003)(46966006)(336012)(8936002)(66616009)(235185007)(478600001)(70586007)(86362001)(7696005)(9686003)(82740400003)(5660300002)(6916009)(33656002)(8676002)(47076005)(55016002)(70206006)(4326008)(82310400003)(6506007)(2906002)(186003)(81166007)(356005)(99936003)(26005)(316002)(52536014); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2021 11:36:12.3746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e82badf2-04cd-49fc-4094-08d8be00c137 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT035.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB2799 X-Spam-Status: No, score=-15.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Joel Hutton via Gcc-patches From: Joel Hutton Reply-To: Joel Hutton Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi all, This patch removes support for the widening subtract operation in the aarch64 backend as it is causing a performance regression. In the following example: #include extern void wdiff( int16_t d[16], uint8_t *restrict pix1, uint8_t *restrict pix2) {    for( int y = 0; y < 4; y++ )   {         for( int x = 0; x < 4; x++ )       d[x + y*4] = pix1[x] - pix2[x];     pix1 += 16;       pix2 += 16;  } The widening minus pattern is recognized and substituted, but cannot be used due to the input vector type chosen in slp vectorization. This results in an attempt to do an 8 byte->8 short widening subtract operation, which is not supported. The issue is documented in PR 98772. [AArch64] Remove backend support for widen-sub This patch removes support for the widening subtract operation in the aarch64 backend as it is causing a performance regression. gcc/ChangeLog:         * config/aarch64/aarch64-simd.md             (vec_widen_subl_lo_): Removed.         (vec_widen_subl_hi_): Removed. gcc/testsuite/ChangeLog:         * gcc.target/aarch64/vect-widen-sub.c: Removed. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 41071b668fd0982f55f9e48510403b9f50fe0f60..c685c512e06917f9cf6bdcffcc41dd091dabfb4e 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3478,30 +3478,6 @@ DONE; }) -(define_expand "vec_widen_subl_lo_" - [(match_operand: 0 "register_operand") - (ANY_EXTEND: (match_operand:VQW 1 "register_operand")) - (ANY_EXTEND: (match_operand:VQW 2 "register_operand"))] - "TARGET_SIMD" -{ - rtx p = aarch64_simd_vect_par_cnst_half (mode, , false); - emit_insn (gen_aarch64_subl_lo_internal (operands[0], operands[1], - operands[2], p)); - DONE; -}) - -(define_expand "vec_widen_subl_hi_" - [(match_operand: 0 "register_operand") - (ANY_EXTEND: (match_operand:VQW 1 "register_operand")) - (ANY_EXTEND: (match_operand:VQW 2 "register_operand"))] - "TARGET_SIMD" -{ - rtx p = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_subl_hi_internal (operands[0], operands[1], - operands[2], p)); - DONE; -}) - (define_expand "aarch64_saddl2" [(match_operand: 0 "register_operand") (match_operand:VQW 1 "register_operand") diff --git a/gcc/testsuite/gcc.target/aarch64/vect-widen-sub.c b/gcc/testsuite/gcc.target/aarch64/vect-widen-sub.c deleted file mode 100644 index a2bed63affbd091977df95a126da1f5b8c1d41d2..0000000000000000000000000000000000000000 --- a/gcc/testsuite/gcc.target/aarch64/vect-widen-sub.c +++ /dev/null @@ -1,92 +0,0 @@ -/* { dg-do run } */ -/* { dg-options "-O3 -save-temps" } */ -#include -#include - -#pragma GCC target "+nosve" - -#define ARR_SIZE 1024 - -/* Should produce an usubl */ -void usub_opt (uint32_t *foo, uint16_t *a, uint16_t *b) -{ - for( int i = 0; i < ARR_SIZE - 3;i=i+4) - { - foo[i] = a[i] - b[i]; - foo[i+1] = a[i+1] - b[i+1]; - foo[i+2] = a[i+2] - b[i+2]; - foo[i+3] = a[i+3] - b[i+3]; - } -} - -__attribute__((optimize (0))) -void usub_nonopt (uint32_t *foo, uint16_t *a, uint16_t *b) -{ - for( int i = 0; i < ARR_SIZE - 3;i=i+4) - { - foo[i] = a[i] - b[i]; - foo[i+1] = a[i+1] - b[i+1]; - foo[i+2] = a[i+2] - b[i+2]; - foo[i+3] = a[i+3] - b[i+3]; - } -} - -/* Should produce an ssubl */ -void ssub_opt (int32_t *foo, int16_t *a, int16_t *b) -{ - for( int i = 0; i < ARR_SIZE - 3;i=i+4) - { - foo[i] = a[i] - b[i]; - foo[i+1] = a[i+1] - b[i+1]; - foo[i+2] = a[i+2] - b[i+2]; - foo[i+3] = a[i+3] - b[i+3]; - } -} - -__attribute__((optimize (0))) -void ssub_nonopt (int32_t *foo, int16_t *a, int16_t *b) -{ - for( int i = 0; i < ARR_SIZE - 3;i=i+4) - { - foo[i] = a[i] - b[i]; - foo[i+1] = a[i+1] - b[i+1]; - foo[i+2] = a[i+2] - b[i+2]; - foo[i+3] = a[i+3] - b[i+3]; - } -} - - -void __attribute__((optimize (0))) -init(uint16_t *a, uint16_t *b) -{ - for( int i = 0; i < ARR_SIZE;i++) - { - a[i] = i; - b[i] = 2*i; - } -} - -int __attribute__((optimize (0))) -main() -{ - uint32_t foo_arr[ARR_SIZE]; - uint32_t bar_arr[ARR_SIZE]; - uint16_t a[ARR_SIZE]; - uint16_t b[ARR_SIZE]; - - init(a, b); - usub_opt(foo_arr, a, b); - usub_nonopt(bar_arr, a, b); - if (memcmp(foo_arr, bar_arr, ARR_SIZE) != 0) - return 1; - ssub_opt((int32_t*) foo_arr, (int16_t*) a, (int16_t*) b); - ssub_nonopt((int32_t*) bar_arr, (int16_t*) a, (int16_t*) b); - if (memcmp(foo_arr, bar_arr, ARR_SIZE) != 0) - return 1; - return 0; -} - -/* { dg-final { scan-assembler-times {\tusubl\t} 1} } */ -/* { dg-final { scan-assembler-times {\tusubl2\t} 1} } */ -/* { dg-final { scan-assembler-times {\tssubl\t} 1} } */ -/* { dg-final { scan-assembler-times {\tssubl2\t} 1} } */