From patchwork Thu Aug 23 07:23:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Malcomson X-Patchwork-Id: 961198 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-484245-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="e5O8apZG"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="S/hWt9f4"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41wx3K3tz4z9s3C for ; Thu, 23 Aug 2018 17:33:15 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :content-type:mime-version:from:to:cc:date:subject:message-id; q=dns; s=default; b=ljZY6xhI0FkF5l912uO2CSEQOqu8+yIgzqWp9x9/0Bk cJDxtjT/fEQUIYEA2+3bDLq1WM9pWZbCDM3ghGPTch+qZXdiHpOrf+d0K5bfWIRO Wi2dhJk0c/kw3zZ/QqBuIgNXFxeAbnHJUIEL7pGHwlcF6zucBqGBJ4+nziuosSak = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :content-type:mime-version:from:to:cc:date:subject:message-id; s=default; bh=oDsGUMw7T0A6TwCpHPVXnYqIXZY=; b=e5O8apZG1qZ8/PW09 1GHQwLWz3tZyvusGvvSTcihiTqeBa7a+Srn55OBxYQ7h+0op/gv49iS0T0VLBWgE 6INBfCHHZxVzsBD19bM+WrC8umq2QZ7zg9DIcU90cOJq2nKgcygn+d3a/diu2lRB 3nzu719G9jABLGL8qi0+RRL6bs= Received: (qmail 51527 invoked by alias); 23 Aug 2018 07:33:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 51513 invoked by uid 89); 23 Aug 2018 07:33:07 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=vas, Matthew, primarily, sk:define_ X-HELO: EUR01-DB5-obe.outbound.protection.outlook.com Received: from mail-db5eur01on0084.outbound.protection.outlook.com (HELO EUR01-DB5-obe.outbound.protection.outlook.com) (104.47.2.84) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 23 Aug 2018 07:33:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=epfAWckDT7/z2Ip83ZSgMo6fAyiBiQFWGsW/sXFkCLg=; b=S/hWt9f4q4tgY6CRr6Z+ZVZWOSvKUolePPFGWZAj7seHVAbyiq2MKBZyTbCpnYW47YKaelEovPTBnxCdcCIo1j4d3eo16uEPCXYwiFJsoeE+5acq4H+7sQp7btr3WzioaJz9/J1FNzmbZVsNGSBkaaWAIFVDTseIBiYjKp2zwLQ= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Matthew.Malcomson@arm.com; Received: from e120487-lin.cambridge.arm.com (217.140.106.49) by AM5PR0801MB2001.eurprd08.prod.outlook.com (2603:10a6:203:4b::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1059.23; Thu, 23 Aug 2018 07:32:56 +0000 MIME-Version: 1.0 From: Matthew Malcomson To: gcc-patches@gcc.gnu.org Cc: Marcus.Shawcroft@arm.com, james.greenhalgh@arm.com, nd@arm.com, Richard.Earnshaw@arm.com Date: Fri, 23 Aug 2018 08:23:34 +0100 Subject: [PATCH][GCC][AARCH64] use "arch_enabled" attribute for aarch64. Message-ID: Received-SPF: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-IsSubscribed: yes Hello, arm.md has some attributes "arch" and "arch_enabled" to aid enabling and disabling insn alternatives based on the architecture being targeted. This patch introduces a similar attribute in the aarch64 backend. The new attribute will be used to enable a new alternative for the atomic_store insn in a future patch, but is an atomic change in itself. The new attribute has values "any", "fp", "fp16", "simd", and "sve". These attribute values have been taken from the pre-existing attributes "fp", "fp16", "simd", and "sve". The standalone "fp" attribute has been reintroduced in terms of the "arch" attribute as it's needed for the xgene1.md scheduling file -- the use in this file can't be changed to check for `(eq_attr "arch" "fp")` as the file is reused by the arm.md machine description whose 'arch' attribute doesn't have an 'fp' value. Full bootstrap and regression test done on aarch64. Ok for trunk? I don't have commit rights, so could someone commit it if accepted. gcc/ChangeLog: 2018-08-23 Matthew Malcomson * config/aarch64/aarch64.md (arches): New enum. (arch): New enum attr. (arch_enabled): New attr. (enabled): Now uses arch_enabled only. (simd, sve, fp16): Removed attribute. (fp): Attr now defined in terms of 'arch'. (*mov_aarch64, *movsi_aarch64, *movdi_aarch64, *movti_aarch64, *movhf_aarch64, 2, 3, 3): Merge 'fp' and 'simd' attributes into 'arch'. (*movsf_aarch64, *movdf_aarch64, *movtf_aarch64, *add3_aarch64, subdi3, neg2, 3, one_cmpl2, *_one_cmpl3, *xor_one_cmpl3, *aarch64_ashl_sisd_or_int_3, *aarch64_lshr_sisd_or_int_3, *aarch64_ashr_sisd_or_int_3, *aarch64_sisd_ushl): Convert use of 'simd' attribute into 'arch'. (load_pair_sw_, load_pair_dw_, store_pair_sw_, store_pair_dw_): Convert use of 'fp' attribute to 'arch'. * config/aarch64/aarch64-simd.md (move_lo_quad_internal_, move_lo_quad_internal_): (different modes) Merge 'fp' and 'simd' into 'arch'. (move_lo_quad_internal_be_, move_lo_quad_internal_be_): (different modes) Merge 'fp' and 'simd' into 'arch'. (*aarch64_combinez, *aarch64_combinez_be): Merge 'fp' and 'simd' into 'arch'. ############### Attachment also inlined for ease of reply ############### diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5591c7b5a6bd7783c2b227add3e5a89d1a188f69..bea1c14e8ddabc4175be10790cd839c3a3852dab 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1352,9 +1352,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_" @@ -1368,9 +1367,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_be_" @@ -1384,9 +1382,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_be_" @@ -1400,9 +1397,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_expand "move_lo_quad_" @@ -3114,8 +3110,7 @@ fmov\t%d0, %1 ldr\\t%d0, %1" [(set_attr "type" "neon_move, neon_from_gp, neon_load1_1reg") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*")] + (set_attr "arch" "simd,fp,simd")] ) (define_insn "*aarch64_combinez_be" @@ -3129,8 +3124,7 @@ fmov\t%d0, %1 ldr\\t%d0, %1" [(set_attr "type" "neon_move, neon_from_gp, neon_load1_1reg") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*")] + (set_attr "arch" "simd,fp,simd")] ) (define_expand "aarch64_combine" diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 955bf1814b92d2bbf72d46bb2050998385174200..52ad814aafa8645342342cc6d67084af57e4b343 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -237,41 +237,51 @@ ;; FP or SIMD registers then the pattern predicate should include TARGET_FLOAT ;; or TARGET_SIMD. -;; Attribute that specifies whether or not the instruction touches fp -;; registers. When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_FLOAT. -(define_attr "fp" "no,yes" (const_string "no")) +;; Attributes of the architecture required to support the instruction (or +;; alternative). This attribute is used to compute attribute "enabled", use type +;; "any" to enable an alternative in all cases. -;; Attribute that specifies whether or not the instruction touches half -;; precision fp registers. When this is set to yes for an alternative, -;; that alternative will be disabled when !TARGET_FP_F16INST. -(define_attr "fp16" "no,yes" (const_string "no")) +(define_enum "arches" [ any fp simd sve fp16]) -;; Attribute that specifies whether or not the instruction touches simd -;; registers. When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_SIMD. -(define_attr "simd" "no,yes" (const_string "no")) +(define_enum_attr "arch" "arches" (const_string "any")) -;; Attribute that specifies whether or not the instruction uses SVE. -;; When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_SVE. -(define_attr "sve" "no,yes" (const_string "no")) +;; [For compatibility with Arm in pipeline models] +;; Attribute that specifies whether or not the instruction touches fp +;; registers. +;; Note that this attribute is not used anywhere in either the arm or aarch64 +;; backends except in the scheduling description for xgene1. In that +;; scheduling description this attribute is used to subclass the load_4 and +;; load_8 types. +(define_attr "fp" "no,yes" + (if_then_else + (eq_attr "arch" "fp") + (const_string "yes") + (const_string "no"))) + +(define_attr "arch_enabled" "no,yes" + (if_then_else + (ior + (eq_attr "arch" "any") + + (and (eq_attr "arch" "fp") + (match_test "TARGET_FLOAT")) + + (and (eq_attr "arch" "simd") + (match_test "TARGET_SIMD")) + + (and (eq_attr "arch" "fp16") + (match_test "TARGET_FP_F16INST")) + + (and (eq_attr "arch" "sve") + (match_test "TARGET_SVE"))) + (const_string "yes") + (const_string "no"))) ;; Attribute that controls whether an alternative is enabled or not. ;; Currently it is only used to disable alternatives which touch fp or simd -;; registers when -mgeneral-regs-only is specified. -(define_attr "enabled" "no,yes" - (cond [(ior - (and (eq_attr "fp" "yes") - (eq (symbol_ref "TARGET_FLOAT") (const_int 0))) - (and (eq_attr "simd" "yes") - (eq (symbol_ref "TARGET_SIMD") (const_int 0))) - (and (eq_attr "fp16" "yes") - (eq (symbol_ref "TARGET_FP_F16INST") (const_int 0))) - (and (eq_attr "sve" "yes") - (eq (symbol_ref "TARGET_SVE") (const_int 0)))) - (const_string "no") - ] (const_string "yes"))) +;; registers when -mgeneral-regs-only is specified or to require a special +;; architecture support. +(define_attr "enabled" "no,yes" (attr "arch_enabled")) ;; Attribute that specifies whether we are dealing with a branch to a ;; label that is far away, i.e. further away than the maximum/minimum @@ -987,8 +997,7 @@ ;; The "mov_imm" type for CNT is just a placeholder. [(set_attr "type" "mov_reg,mov_imm,neon_move,mov_imm,load_4,load_4,store_4, store_4,neon_to_gp,neon_from_gp,neon_dup") - (set_attr "simd" "*,*,yes,*,*,*,*,*,yes,yes,yes") - (set_attr "sve" "*,*,*,yes,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,simd,sve,*,*,*,*,simd,simd,simd")] ) (define_expand "mov" @@ -1047,9 +1056,7 @@ ;; The "mov_imm" type for CNT is just a placeholder. [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,load_4, load_4,store_4,store_4,adr,adr,f_mcr,f_mrc,fmov,neon_move") - (set_attr "fp" "*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") - (set_attr "sve" "*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] ) (define_insn_and_split "*movdi_aarch64" @@ -1086,9 +1093,7 @@ [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,mov_imm, load_8,load_8,store_8,store_8,adr,adr,f_mcr,f_mrc,fmov, neon_move") - (set_attr "fp" "*,*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") - (set_attr "sve" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] ) (define_insn "insv_imm" @@ -1141,8 +1146,7 @@ load_16,store_16,store_16,\ load_16,store_16") (set_attr "length" "8,8,8,4,4,4,4,4,4") - (set_attr "simd" "*,*,*,yes,*,*,*,*,*") - (set_attr "fp" "*,*,*,*,*,*,*,yes,yes")] + (set_attr "arch" "*,*,*,simd,*,*,*,fp,fp")] ) ;; Split a TImode register-register or register-immediate move into @@ -1196,8 +1200,7 @@ mov\\t%w0, %w1" [(set_attr "type" "neon_move,f_mcr,neon_move,neon_to_gp, neon_move,fconsts, \ neon_move,f_loads,f_stores,load_4,store_4,mov_reg") - (set_attr "simd" "yes,*,yes,yes,yes,*,yes,*,*,*,*,*") - (set_attr "fp16" "*,yes,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,fp16,simd,simd,simd,fp16,simd,*,*,*,*,*")] ) (define_insn "*movsf_aarch64" @@ -1221,7 +1224,7 @@ [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,neon_move,\ f_loads,f_stores,load_4,store_4,mov_reg,\ fconsts") - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] ) (define_insn "*movdf_aarch64" @@ -1245,7 +1248,7 @@ [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,neon_move,\ f_loadd,f_stored,load_8,store_8,mov_reg,\ fconstd") - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] ) (define_split @@ -1290,7 +1293,7 @@ [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\ f_loadd,f_stored,load_16,store_16,store_16") (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4") - (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,simd,*,*,*,*,*,*")] ) (define_split @@ -1337,7 +1340,7 @@ ldp\\t%w0, %w2, %1 ldp\\t%s0, %s2, %1" [(set_attr "type" "load_8,neon_load1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Storing different modes that can still be merged @@ -1354,7 +1357,7 @@ ldp\\t%x0, %x2, %1 ldp\\t%d0, %d2, %1" [(set_attr "type" "load_16,neon_load1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Operands 0 and 2 are tied together by the final condition; so we allow @@ -1372,7 +1375,7 @@ stp\\t%w1, %w3, %0 stp\\t%s1, %s3, %0" [(set_attr "type" "store_8,neon_store1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Storing different modes that can still be merged @@ -1389,7 +1392,7 @@ stp\\t%x1, %x3, %0 stp\\t%d1, %d3, %0" [(set_attr "type" "store_16,neon_store1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Load pair with post-index writeback. This is primarily used in function @@ -1615,7 +1618,7 @@ * return aarch64_output_sve_addvl_addpl (operands[0], operands[1], operands[2]);" ;; The "alu_imm" type for ADDVL/ADDPL is just a placeholder. [(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm,multiple,alu_imm") - (set_attr "simd" "*,*,yes,*,*,*")] + (set_attr "arch" "*,*,simd,*,*,*")] ) ;; zero_extend version of above @@ -2618,7 +2621,7 @@ sub\\t%x0, %x1, %x2 sub\\t%d0, %d1, %d2" [(set_attr "type" "alu_sreg, neon_sub") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_expand "subv4" @@ -3225,7 +3228,7 @@ neg\\t%0, %1 neg\\t%0, %1" [(set_attr "type" "alu_sreg, neon_neg") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) ;; zero_extend version of above @@ -4070,7 +4073,7 @@ \\t%0, %1, %2 \\t%0., %1., %2." [(set_attr "type" "logic_reg,logic_imm,neon_logic") - (set_attr "simd" "*,*,yes")] + (set_attr "arch" "*,*,simd")] ) ;; zero_extend version of above @@ -4204,7 +4207,7 @@ mvn\\t%0, %1 mvn\\t%0.8b, %1.8b" [(set_attr "type" "logic_reg,neon_logic") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*one_cmpl_2" @@ -4227,7 +4230,7 @@ \\t%0, %2, %1 \\t%0., %2., %1." [(set_attr "type" "logic_reg,neon_logic") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*_one_cmplsidi3_ze" @@ -4267,7 +4270,7 @@ (set (match_dup 0) (not:GPI (match_dup 0)))] "" [(set_attr "type" "logic_reg,multiple") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*and_one_cmpl3_compare0" @@ -4811,8 +4814,8 @@ lsl\t%0, %1, %2 shl\t%0, %1, %2 ushl\t%0, %1, %2" - [(set_attr "simd" "no,no,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm, neon_shift_reg")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm, neon_shift_reg") + (set_attr "arch" "*,*,simd,simd")] ) ;; Logical right shift using SISD or Integer instruction @@ -4829,8 +4832,8 @@ ushr\t%0, %1, %2 # #" - [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg") + (set_attr "arch" "*,*,simd,simd,simd")] ) (define_split @@ -4877,8 +4880,8 @@ sshr\t%0, %1, %2 # #" - [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg") + (set_attr "arch" "*,*,simd,simd,simd")] ) (define_split @@ -4918,8 +4921,7 @@ UNSPEC_SISD_USHL))] "TARGET_SIMD" "ushl\t%d0, %d1, %d2" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_ushl_2s" @@ -4929,8 +4931,7 @@ UNSPEC_USHL_2S))] "TARGET_SIMD" "ushl\t%0.2s, %1.2s, %2.2s" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sisd_sshl" @@ -4940,8 +4941,7 @@ UNSPEC_SISD_SSHL))] "TARGET_SIMD" "sshl\t%d0, %d1, %d2" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sshl_2s" @@ -4951,8 +4951,7 @@ UNSPEC_SSHL_2S))] "TARGET_SIMD" "sshl\t%0.2s, %1.2s, %2.2s" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sisd_neg_qi" @@ -4961,8 +4960,7 @@ UNSPEC_SISD_NEG))] "TARGET_SIMD" "neg\t%d0, %d1" - [(set_attr "simd" "yes") - (set_attr "type" "neon_neg")] + [(set_attr "type" "neon_neg")] ) ;; Rotate right @@ -5598,9 +5596,8 @@ "@ cvtf\t%0, %1 cvtf\t%0, %1" - [(set_attr "simd" "yes,no") - (set_attr "fp" "no,yes") - (set_attr "type" "neon_int_to_fp_,f_cvti2f")] + [(set_attr "type" "neon_int_to_fp_,f_cvti2f") + (set_attr "arch" "simd,fp")] ) (define_insn "2" @@ -5685,8 +5682,7 @@ \t%0, %1, #%2 \t%0, %1, #%2" [(set_attr "type" "f_cvtf2i, neon_fp_to_int_") - (set_attr "fp" "yes, *") - (set_attr "simd" "*, yes")] + (set_attr "arch" "fp,simd")] ) (define_insn "3" @@ -5699,8 +5695,7 @@ \t%0, %1, #%2 \t%0, %1, #%2" [(set_attr "type" "f_cvti2f, neon_int_to_fp_") - (set_attr "fp" "yes, *") - (set_attr "simd" "*, yes")] + (set_attr "arch" "fp,simd")] ) (define_insn "hf3" diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5591c7b5a6bd7783c2b227add3e5a89d1a188f69..bea1c14e8ddabc4175be10790cd839c3a3852dab 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1352,9 +1352,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_" @@ -1368,9 +1367,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_be_" @@ -1384,9 +1382,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_be_" @@ -1400,9 +1397,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_expand "move_lo_quad_" @@ -3114,8 +3110,7 @@ fmov\t%d0, %1 ldr\\t%d0, %1" [(set_attr "type" "neon_move, neon_from_gp, neon_load1_1reg") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*")] + (set_attr "arch" "simd,fp,simd")] ) (define_insn "*aarch64_combinez_be" @@ -3129,8 +3124,7 @@ fmov\t%d0, %1 ldr\\t%d0, %1" [(set_attr "type" "neon_move, neon_from_gp, neon_load1_1reg") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*")] + (set_attr "arch" "simd,fp,simd")] ) (define_expand "aarch64_combine" diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 955bf1814b92d2bbf72d46bb2050998385174200..52ad814aafa8645342342cc6d67084af57e4b343 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -237,41 +237,51 @@ ;; FP or SIMD registers then the pattern predicate should include TARGET_FLOAT ;; or TARGET_SIMD. -;; Attribute that specifies whether or not the instruction touches fp -;; registers. When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_FLOAT. -(define_attr "fp" "no,yes" (const_string "no")) +;; Attributes of the architecture required to support the instruction (or +;; alternative). This attribute is used to compute attribute "enabled", use type +;; "any" to enable an alternative in all cases. -;; Attribute that specifies whether or not the instruction touches half -;; precision fp registers. When this is set to yes for an alternative, -;; that alternative will be disabled when !TARGET_FP_F16INST. -(define_attr "fp16" "no,yes" (const_string "no")) +(define_enum "arches" [ any fp simd sve fp16]) -;; Attribute that specifies whether or not the instruction touches simd -;; registers. When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_SIMD. -(define_attr "simd" "no,yes" (const_string "no")) +(define_enum_attr "arch" "arches" (const_string "any")) -;; Attribute that specifies whether or not the instruction uses SVE. -;; When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_SVE. -(define_attr "sve" "no,yes" (const_string "no")) +;; [For compatibility with Arm in pipeline models] +;; Attribute that specifies whether or not the instruction touches fp +;; registers. +;; Note that this attribute is not used anywhere in either the arm or aarch64 +;; backends except in the scheduling description for xgene1. In that +;; scheduling description this attribute is used to subclass the load_4 and +;; load_8 types. +(define_attr "fp" "no,yes" + (if_then_else + (eq_attr "arch" "fp") + (const_string "yes") + (const_string "no"))) + +(define_attr "arch_enabled" "no,yes" + (if_then_else + (ior + (eq_attr "arch" "any") + + (and (eq_attr "arch" "fp") + (match_test "TARGET_FLOAT")) + + (and (eq_attr "arch" "simd") + (match_test "TARGET_SIMD")) + + (and (eq_attr "arch" "fp16") + (match_test "TARGET_FP_F16INST")) + + (and (eq_attr "arch" "sve") + (match_test "TARGET_SVE"))) + (const_string "yes") + (const_string "no"))) ;; Attribute that controls whether an alternative is enabled or not. ;; Currently it is only used to disable alternatives which touch fp or simd -;; registers when -mgeneral-regs-only is specified. -(define_attr "enabled" "no,yes" - (cond [(ior - (and (eq_attr "fp" "yes") - (eq (symbol_ref "TARGET_FLOAT") (const_int 0))) - (and (eq_attr "simd" "yes") - (eq (symbol_ref "TARGET_SIMD") (const_int 0))) - (and (eq_attr "fp16" "yes") - (eq (symbol_ref "TARGET_FP_F16INST") (const_int 0))) - (and (eq_attr "sve" "yes") - (eq (symbol_ref "TARGET_SVE") (const_int 0)))) - (const_string "no") - ] (const_string "yes"))) +;; registers when -mgeneral-regs-only is specified or to require a special +;; architecture support. +(define_attr "enabled" "no,yes" (attr "arch_enabled")) ;; Attribute that specifies whether we are dealing with a branch to a ;; label that is far away, i.e. further away than the maximum/minimum @@ -987,8 +997,7 @@ ;; The "mov_imm" type for CNT is just a placeholder. [(set_attr "type" "mov_reg,mov_imm,neon_move,mov_imm,load_4,load_4,store_4, store_4,neon_to_gp,neon_from_gp,neon_dup") - (set_attr "simd" "*,*,yes,*,*,*,*,*,yes,yes,yes") - (set_attr "sve" "*,*,*,yes,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,simd,sve,*,*,*,*,simd,simd,simd")] ) (define_expand "mov" @@ -1047,9 +1056,7 @@ ;; The "mov_imm" type for CNT is just a placeholder. [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,load_4, load_4,store_4,store_4,adr,adr,f_mcr,f_mrc,fmov,neon_move") - (set_attr "fp" "*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") - (set_attr "sve" "*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] ) (define_insn_and_split "*movdi_aarch64" @@ -1086,9 +1093,7 @@ [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,mov_imm, load_8,load_8,store_8,store_8,adr,adr,f_mcr,f_mrc,fmov, neon_move") - (set_attr "fp" "*,*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") - (set_attr "sve" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] ) (define_insn "insv_imm" @@ -1141,8 +1146,7 @@ load_16,store_16,store_16,\ load_16,store_16") (set_attr "length" "8,8,8,4,4,4,4,4,4") - (set_attr "simd" "*,*,*,yes,*,*,*,*,*") - (set_attr "fp" "*,*,*,*,*,*,*,yes,yes")] + (set_attr "arch" "*,*,*,simd,*,*,*,fp,fp")] ) ;; Split a TImode register-register or register-immediate move into @@ -1196,8 +1200,7 @@ mov\\t%w0, %w1" [(set_attr "type" "neon_move,f_mcr,neon_move,neon_to_gp, neon_move,fconsts, \ neon_move,f_loads,f_stores,load_4,store_4,mov_reg") - (set_attr "simd" "yes,*,yes,yes,yes,*,yes,*,*,*,*,*") - (set_attr "fp16" "*,yes,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,fp16,simd,simd,simd,fp16,simd,*,*,*,*,*")] ) (define_insn "*movsf_aarch64" @@ -1221,7 +1224,7 @@ [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,neon_move,\ f_loads,f_stores,load_4,store_4,mov_reg,\ fconsts") - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] ) (define_insn "*movdf_aarch64" @@ -1245,7 +1248,7 @@ [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,neon_move,\ f_loadd,f_stored,load_8,store_8,mov_reg,\ fconstd") - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] ) (define_split @@ -1290,7 +1293,7 @@ [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\ f_loadd,f_stored,load_16,store_16,store_16") (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4") - (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,simd,*,*,*,*,*,*")] ) (define_split @@ -1337,7 +1340,7 @@ ldp\\t%w0, %w2, %1 ldp\\t%s0, %s2, %1" [(set_attr "type" "load_8,neon_load1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Storing different modes that can still be merged @@ -1354,7 +1357,7 @@ ldp\\t%x0, %x2, %1 ldp\\t%d0, %d2, %1" [(set_attr "type" "load_16,neon_load1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Operands 0 and 2 are tied together by the final condition; so we allow @@ -1372,7 +1375,7 @@ stp\\t%w1, %w3, %0 stp\\t%s1, %s3, %0" [(set_attr "type" "store_8,neon_store1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Storing different modes that can still be merged @@ -1389,7 +1392,7 @@ stp\\t%x1, %x3, %0 stp\\t%d1, %d3, %0" [(set_attr "type" "store_16,neon_store1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Load pair with post-index writeback. This is primarily used in function @@ -1615,7 +1618,7 @@ * return aarch64_output_sve_addvl_addpl (operands[0], operands[1], operands[2]);" ;; The "alu_imm" type for ADDVL/ADDPL is just a placeholder. [(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm,multiple,alu_imm") - (set_attr "simd" "*,*,yes,*,*,*")] + (set_attr "arch" "*,*,simd,*,*,*")] ) ;; zero_extend version of above @@ -2618,7 +2621,7 @@ sub\\t%x0, %x1, %x2 sub\\t%d0, %d1, %d2" [(set_attr "type" "alu_sreg, neon_sub") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_expand "subv4" @@ -3225,7 +3228,7 @@ neg\\t%0, %1 neg\\t%0, %1" [(set_attr "type" "alu_sreg, neon_neg") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) ;; zero_extend version of above @@ -4070,7 +4073,7 @@ \\t%0, %1, %2 \\t%0., %1., %2." [(set_attr "type" "logic_reg,logic_imm,neon_logic") - (set_attr "simd" "*,*,yes")] + (set_attr "arch" "*,*,simd")] ) ;; zero_extend version of above @@ -4204,7 +4207,7 @@ mvn\\t%0, %1 mvn\\t%0.8b, %1.8b" [(set_attr "type" "logic_reg,neon_logic") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*one_cmpl_2" @@ -4227,7 +4230,7 @@ \\t%0, %2, %1 \\t%0., %2., %1." [(set_attr "type" "logic_reg,neon_logic") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*_one_cmplsidi3_ze" @@ -4267,7 +4270,7 @@ (set (match_dup 0) (not:GPI (match_dup 0)))] "" [(set_attr "type" "logic_reg,multiple") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*and_one_cmpl3_compare0" @@ -4811,8 +4814,8 @@ lsl\t%0, %1, %2 shl\t%0, %1, %2 ushl\t%0, %1, %2" - [(set_attr "simd" "no,no,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm, neon_shift_reg")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm, neon_shift_reg") + (set_attr "arch" "*,*,simd,simd")] ) ;; Logical right shift using SISD or Integer instruction @@ -4829,8 +4832,8 @@ ushr\t%0, %1, %2 # #" - [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg") + (set_attr "arch" "*,*,simd,simd,simd")] ) (define_split @@ -4877,8 +4880,8 @@ sshr\t%0, %1, %2 # #" - [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg") + (set_attr "arch" "*,*,simd,simd,simd")] ) (define_split @@ -4918,8 +4921,7 @@ UNSPEC_SISD_USHL))] "TARGET_SIMD" "ushl\t%d0, %d1, %d2" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_ushl_2s" @@ -4929,8 +4931,7 @@ UNSPEC_USHL_2S))] "TARGET_SIMD" "ushl\t%0.2s, %1.2s, %2.2s" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sisd_sshl" @@ -4940,8 +4941,7 @@ UNSPEC_SISD_SSHL))] "TARGET_SIMD" "sshl\t%d0, %d1, %d2" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sshl_2s" @@ -4951,8 +4951,7 @@ UNSPEC_SSHL_2S))] "TARGET_SIMD" "sshl\t%0.2s, %1.2s, %2.2s" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sisd_neg_qi" @@ -4961,8 +4960,7 @@ UNSPEC_SISD_NEG))] "TARGET_SIMD" "neg\t%d0, %d1" - [(set_attr "simd" "yes") - (set_attr "type" "neon_neg")] + [(set_attr "type" "neon_neg")] ) ;; Rotate right @@ -5598,9 +5596,8 @@ "@ cvtf\t%0, %1 cvtf\t%0, %1" - [(set_attr "simd" "yes,no") - (set_attr "fp" "no,yes") - (set_attr "type" "neon_int_to_fp_,f_cvti2f")] + [(set_attr "type" "neon_int_to_fp_,f_cvti2f") + (set_attr "arch" "simd,fp")] ) (define_insn "2" @@ -5685,8 +5682,7 @@ \t%0, %1, #%2 \t%0, %1, #%2" [(set_attr "type" "f_cvtf2i, neon_fp_to_int_") - (set_attr "fp" "yes, *") - (set_attr "simd" "*, yes")] + (set_attr "arch" "fp,simd")] ) (define_insn "3" @@ -5699,8 +5695,7 @@ \t%0, %1, #%2 \t%0, %1, #%2" [(set_attr "type" "f_cvti2f, neon_int_to_fp_") - (set_attr "fp" "yes, *") - (set_attr "simd" "*, yes")] + (set_attr "arch" "fp,simd")] ) (define_insn "hf3"