| Message ID | AM5PR0801MB200111203FA715D92C26DA5BE0370@AM5PR0801MB2001.eurprd08.prod.outlook.com |
|---|---|
| State | New |
| Headers | show |
| Series | [AARCH64] use "arch_enabled" attribute for aarch64. | expand |
On 23/08/18 08:23, Matthew Malcomson wrote: > Hello, > > arm.md has some attributes "arch" and "arch_enabled" to aid enabling and > disabling insn alternatives based on the architecture being targeted. > This patch introduces a similar attribute in the aarch64 backend. > The new attribute will be used to enable a new alternative for the atomic_store > insn in a future patch, but is an atomic change in itself. > > The new attribute has values "any", "fp", "fp16", "simd", and "sve". > These attribute values have been taken from the pre-existing attributes "fp", > "fp16", "simd", and "sve". > The standalone "fp" attribute has been reintroduced in terms of the "arch" > attribute as it's needed for the xgene1.md scheduling file -- the use in this > file can't be changed to check for `(eq_attr "arch" "fp")` as the file is > reused by the arm.md machine description whose 'arch' attribute doesn't have an > 'fp' value. > > > Full bootstrap and regression test done on aarch64. > > Ok for trunk? > I don't have commit rights, so could someone commit it if accepted. > Committed. Thanks, R. > > gcc/ChangeLog: > > 2018-08-23 Matthew Malcomson <matthew.malcomson@arm.com> > > * config/aarch64/aarch64.md (arches): New enum. > (arch): New enum attr. > (arch_enabled): New attr. > (enabled): Now uses arch_enabled only. > (simd, sve, fp16): Removed attribute. > (fp): Attr now defined in terms of 'arch'. > (*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64, *movti_aarch64, > *movhf_aarch64, <optab><fcvt_target><GPF:mode>2, > <FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3, > <FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3): Merge 'fp' and 'simd' > attributes into 'arch'. > (*movsf_aarch64, *movdf_aarch64, *movtf_aarch64, *add<mode>3_aarch64, > subdi3, neg<mode>2, <optab><mode>3, one_cmpl<mode>2, > *<NLOGICAL:optab>_one_cmpl<mode>3, *xor_one_cmpl<mode>3, > *aarch64_ashl_sisd_or_int_<mode>3, *aarch64_lshr_sisd_or_int_<mode>3, > *aarch64_ashr_sisd_or_int_<mode>3, *aarch64_sisd_ushl): Convert use of > 'simd' attribute into 'arch'. > (load_pair_sw_<SX:mode><SX2:mode>, load_pair_dw_<DX:mode><DX2:mode>, > store_pair_sw_<SX:mode><SX2:mode>, store_pair_dw_<DX:mode><DX2:mode>): > Convert use of 'fp' attribute to 'arch'. > * config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>, > move_lo_quad_internal_<mode>): (different modes) Merge 'fp' and 'simd' > into 'arch'. > (move_lo_quad_internal_be_<mode>, move_lo_quad_internal_be_<mode>): > (different modes) Merge 'fp' and 'simd' into 'arch'. > (*aarch64_combinez<mode>, *aarch64_combinez_be<mode>): Merge 'fp' and > 'simd' into 'arch'. > > > ############### Attachment also inlined for ease of reply ############### > > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index 5591c7b5a6bd7783c2b227add3e5a89d1a188f69..bea1c14e8ddabc4175be10790cd839c3a3852dab 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -1352,9 +1352,8 @@ > fmov\\t%d0, %1 > dup\\t%d0, %1" > [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*") > - (set_attr "length" "4")] > + (set_attr "length" "4") > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_insn "move_lo_quad_internal_<mode>" > @@ -1368,9 +1367,8 @@ > fmov\\t%d0, %1 > dup\\t%d0, %1" > [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*") > - (set_attr "length" "4")] > + (set_attr "length" "4") > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_insn "move_lo_quad_internal_be_<mode>" > @@ -1384,9 +1382,8 @@ > fmov\\t%d0, %1 > dup\\t%d0, %1" > [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*") > - (set_attr "length" "4")] > + (set_attr "length" "4") > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_insn "move_lo_quad_internal_be_<mode>" > @@ -1400,9 +1397,8 @@ > fmov\\t%d0, %1 > dup\\t%d0, %1" > [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*") > - (set_attr "length" "4")] > + (set_attr "length" "4") > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_expand "move_lo_quad_<mode>" > @@ -3114,8 +3110,7 @@ > fmov\t%d0, %1 > ldr\\t%d0, %1" > [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*")] > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_insn "*aarch64_combinez_be<mode>" > @@ -3129,8 +3124,7 @@ > fmov\t%d0, %1 > ldr\\t%d0, %1" > [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*")] > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_expand "aarch64_combine<mode>" > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 955bf1814b92d2bbf72d46bb2050998385174200..52ad814aafa8645342342cc6d67084af57e4b343 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -237,41 +237,51 @@ > ;; FP or SIMD registers then the pattern predicate should include TARGET_FLOAT > ;; or TARGET_SIMD. > > -;; Attribute that specifies whether or not the instruction touches fp > -;; registers. When this is set to yes for an alternative, that alternative > -;; will be disabled when !TARGET_FLOAT. > -(define_attr "fp" "no,yes" (const_string "no")) > +;; Attributes of the architecture required to support the instruction (or > +;; alternative). This attribute is used to compute attribute "enabled", use type > +;; "any" to enable an alternative in all cases. > > -;; Attribute that specifies whether or not the instruction touches half > -;; precision fp registers. When this is set to yes for an alternative, > -;; that alternative will be disabled when !TARGET_FP_F16INST. > -(define_attr "fp16" "no,yes" (const_string "no")) > +(define_enum "arches" [ any fp simd sve fp16]) > > -;; Attribute that specifies whether or not the instruction touches simd > -;; registers. When this is set to yes for an alternative, that alternative > -;; will be disabled when !TARGET_SIMD. > -(define_attr "simd" "no,yes" (const_string "no")) > +(define_enum_attr "arch" "arches" (const_string "any")) > > -;; Attribute that specifies whether or not the instruction uses SVE. > -;; When this is set to yes for an alternative, that alternative > -;; will be disabled when !TARGET_SVE. > -(define_attr "sve" "no,yes" (const_string "no")) > +;; [For compatibility with Arm in pipeline models] > +;; Attribute that specifies whether or not the instruction touches fp > +;; registers. > +;; Note that this attribute is not used anywhere in either the arm or aarch64 > +;; backends except in the scheduling description for xgene1. In that > +;; scheduling description this attribute is used to subclass the load_4 and > +;; load_8 types. > +(define_attr "fp" "no,yes" > + (if_then_else > + (eq_attr "arch" "fp") > + (const_string "yes") > + (const_string "no"))) > + > +(define_attr "arch_enabled" "no,yes" > + (if_then_else > + (ior > + (eq_attr "arch" "any") > + > + (and (eq_attr "arch" "fp") > + (match_test "TARGET_FLOAT")) > + > + (and (eq_attr "arch" "simd") > + (match_test "TARGET_SIMD")) > + > + (and (eq_attr "arch" "fp16") > + (match_test "TARGET_FP_F16INST")) > + > + (and (eq_attr "arch" "sve") > + (match_test "TARGET_SVE"))) > + (const_string "yes") > + (const_string "no"))) > > ;; Attribute that controls whether an alternative is enabled or not. > ;; Currently it is only used to disable alternatives which touch fp or simd > -;; registers when -mgeneral-regs-only is specified. > -(define_attr "enabled" "no,yes" > - (cond [(ior > - (and (eq_attr "fp" "yes") > - (eq (symbol_ref "TARGET_FLOAT") (const_int 0))) > - (and (eq_attr "simd" "yes") > - (eq (symbol_ref "TARGET_SIMD") (const_int 0))) > - (and (eq_attr "fp16" "yes") > - (eq (symbol_ref "TARGET_FP_F16INST") (const_int 0))) > - (and (eq_attr "sve" "yes") > - (eq (symbol_ref "TARGET_SVE") (const_int 0)))) > - (const_string "no") > - ] (const_string "yes"))) > +;; registers when -mgeneral-regs-only is specified or to require a special > +;; architecture support. > +(define_attr "enabled" "no,yes" (attr "arch_enabled")) > > ;; Attribute that specifies whether we are dealing with a branch to a > ;; label that is far away, i.e. further away than the maximum/minimum > @@ -987,8 +997,7 @@ > ;; The "mov_imm" type for CNT is just a placeholder. > [(set_attr "type" "mov_reg,mov_imm,neon_move,mov_imm,load_4,load_4,store_4, > store_4,neon_to_gp<q>,neon_from_gp<q>,neon_dup") > - (set_attr "simd" "*,*,yes,*,*,*,*,*,yes,yes,yes") > - (set_attr "sve" "*,*,*,yes,*,*,*,*,*,*,*")] > + (set_attr "arch" "*,*,simd,sve,*,*,*,*,simd,simd,simd")] > ) > > (define_expand "mov<mode>" > @@ -1047,9 +1056,7 @@ > ;; The "mov_imm" type for CNT is just a placeholder. > [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,load_4, > load_4,store_4,store_4,adr,adr,f_mcr,f_mrc,fmov,neon_move") > - (set_attr "fp" "*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") > - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") > - (set_attr "sve" "*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] > + (set_attr "arch" "*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] > ) > > (define_insn_and_split "*movdi_aarch64" > @@ -1086,9 +1093,7 @@ > [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,mov_imm, > load_8,load_8,store_8,store_8,adr,adr,f_mcr,f_mrc,fmov, > neon_move") > - (set_attr "fp" "*,*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") > - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") > - (set_attr "sve" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] > + (set_attr "arch" "*,*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] > ) > > (define_insn "insv_imm<mode>" > @@ -1141,8 +1146,7 @@ > load_16,store_16,store_16,\ > load_16,store_16") > (set_attr "length" "8,8,8,4,4,4,4,4,4") > - (set_attr "simd" "*,*,*,yes,*,*,*,*,*") > - (set_attr "fp" "*,*,*,*,*,*,*,yes,yes")] > + (set_attr "arch" "*,*,*,simd,*,*,*,fp,fp")] > ) > > ;; Split a TImode register-register or register-immediate move into > @@ -1196,8 +1200,7 @@ > mov\\t%w0, %w1" > [(set_attr "type" "neon_move,f_mcr,neon_move,neon_to_gp, neon_move,fconsts, \ > neon_move,f_loads,f_stores,load_4,store_4,mov_reg") > - (set_attr "simd" "yes,*,yes,yes,yes,*,yes,*,*,*,*,*") > - (set_attr "fp16" "*,yes,*,*,*,yes,*,*,*,*,*,*")] > + (set_attr "arch" "simd,fp16,simd,simd,simd,fp16,simd,*,*,*,*,*")] > ) > > (define_insn "*movsf_aarch64" > @@ -1221,7 +1224,7 @@ > [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,neon_move,\ > f_loads,f_stores,load_4,store_4,mov_reg,\ > fconsts") > - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] > + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] > ) > > (define_insn "*movdf_aarch64" > @@ -1245,7 +1248,7 @@ > [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,neon_move,\ > f_loadd,f_stored,load_8,store_8,mov_reg,\ > fconstd") > - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] > + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] > ) > > (define_split > @@ -1290,7 +1293,7 @@ > [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\ > f_loadd,f_stored,load_16,store_16,store_16") > (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4") > - (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")] > + (set_attr "arch" "simd,*,*,*,simd,*,*,*,*,*,*")] > ) > > (define_split > @@ -1337,7 +1340,7 @@ > ldp\\t%w0, %w2, %1 > ldp\\t%s0, %s2, %1" > [(set_attr "type" "load_8,neon_load1_2reg") > - (set_attr "fp" "*,yes")] > + (set_attr "arch" "*,fp")] > ) > > ;; Storing different modes that can still be merged > @@ -1354,7 +1357,7 @@ > ldp\\t%x0, %x2, %1 > ldp\\t%d0, %d2, %1" > [(set_attr "type" "load_16,neon_load1_2reg") > - (set_attr "fp" "*,yes")] > + (set_attr "arch" "*,fp")] > ) > > ;; Operands 0 and 2 are tied together by the final condition; so we allow > @@ -1372,7 +1375,7 @@ > stp\\t%w1, %w3, %0 > stp\\t%s1, %s3, %0" > [(set_attr "type" "store_8,neon_store1_2reg") > - (set_attr "fp" "*,yes")] > + (set_attr "arch" "*,fp")] > ) > > ;; Storing different modes that can still be merged > @@ -1389,7 +1392,7 @@ > stp\\t%x1, %x3, %0 > stp\\t%d1, %d3, %0" > [(set_attr "type" "store_16,neon_store1_2reg") > - (set_attr "fp" "*,yes")] > + (set_attr "arch" "*,fp")] > ) > > ;; Load pair with post-index writeback. This is primarily used in function > @@ -1615,7 +1618,7 @@ > * return aarch64_output_sve_addvl_addpl (operands[0], operands[1], operands[2]);" > ;; The "alu_imm" type for ADDVL/ADDPL is just a placeholder. > [(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm,multiple,alu_imm") > - (set_attr "simd" "*,*,yes,*,*,*")] > + (set_attr "arch" "*,*,simd,*,*,*")] > ) > > ;; zero_extend version of above > @@ -2618,7 +2621,7 @@ > sub\\t%x0, %x1, %x2 > sub\\t%d0, %d1, %d2" > [(set_attr "type" "alu_sreg, neon_sub") > - (set_attr "simd" "*,yes")] > + (set_attr "arch" "*,simd")] > ) > > (define_expand "subv<mode>4" > @@ -3225,7 +3228,7 @@ > neg\\t%<w>0, %<w>1 > neg\\t%<rtn>0<vas>, %<rtn>1<vas>" > [(set_attr "type" "alu_sreg, neon_neg<q>") > - (set_attr "simd" "*,yes")] > + (set_attr "arch" "*,simd")] > ) > > ;; zero_extend version of above > @@ -4070,7 +4073,7 @@ > <logical>\\t%<w>0, %<w>1, %2 > <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>" > [(set_attr "type" "logic_reg,logic_imm,neon_logic") > - (set_attr "simd" "*,*,yes")] > + (set_attr "arch" "*,*,simd")] > ) > > ;; zero_extend version of above > @@ -4204,7 +4207,7 @@ > mvn\\t%<w>0, %<w>1 > mvn\\t%0.8b, %1.8b" > [(set_attr "type" "logic_reg,neon_logic") > - (set_attr "simd" "*,yes")] > + (set_attr "arch" "*,simd")] > ) > > (define_insn "*one_cmpl_<optab><mode>2" > @@ -4227,7 +4230,7 @@ > <NLOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1 > <NLOGICAL:nlogical>\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>" > [(set_attr "type" "logic_reg,neon_logic") > - (set_attr "simd" "*,yes")] > + (set_attr "arch" "*,simd")] > ) > > (define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze" > @@ -4267,7 +4270,7 @@ > (set (match_dup 0) (not:GPI (match_dup 0)))] > "" > [(set_attr "type" "logic_reg,multiple") > - (set_attr "simd" "*,yes")] > + (set_attr "arch" "*,simd")] > ) > > (define_insn "*and_one_cmpl<mode>3_compare0" > @@ -4811,8 +4814,8 @@ > lsl\t%<w>0, %<w>1, %<w>2 > shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2 > ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>" > - [(set_attr "simd" "no,no,yes,yes") > - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")] > + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>") > + (set_attr "arch" "*,*,simd,simd")] > ) > > ;; Logical right shift using SISD or Integer instruction > @@ -4829,8 +4832,8 @@ > ushr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 > # > #" > - [(set_attr "simd" "no,no,yes,yes,yes") > - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] > + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>") > + (set_attr "arch" "*,*,simd,simd,simd")] > ) > > (define_split > @@ -4877,8 +4880,8 @@ > sshr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 > # > #" > - [(set_attr "simd" "no,no,yes,yes,yes") > - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] > + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>") > + (set_attr "arch" "*,*,simd,simd,simd")] > ) > > (define_split > @@ -4918,8 +4921,7 @@ > UNSPEC_SISD_USHL))] > "TARGET_SIMD" > "ushl\t%d0, %d1, %d2" > - [(set_attr "simd" "yes") > - (set_attr "type" "neon_shift_reg")] > + [(set_attr "type" "neon_shift_reg")] > ) > > (define_insn "*aarch64_ushl_2s" > @@ -4929,8 +4931,7 @@ > UNSPEC_USHL_2S))] > "TARGET_SIMD" > "ushl\t%0.2s, %1.2s, %2.2s" > - [(set_attr "simd" "yes") > - (set_attr "type" "neon_shift_reg")] > + [(set_attr "type" "neon_shift_reg")] > ) > > (define_insn "*aarch64_sisd_sshl" > @@ -4940,8 +4941,7 @@ > UNSPEC_SISD_SSHL))] > "TARGET_SIMD" > "sshl\t%d0, %d1, %d2" > - [(set_attr "simd" "yes") > - (set_attr "type" "neon_shift_reg")] > + [(set_attr "type" "neon_shift_reg")] > ) > > (define_insn "*aarch64_sshl_2s" > @@ -4951,8 +4951,7 @@ > UNSPEC_SSHL_2S))] > "TARGET_SIMD" > "sshl\t%0.2s, %1.2s, %2.2s" > - [(set_attr "simd" "yes") > - (set_attr "type" "neon_shift_reg")] > + [(set_attr "type" "neon_shift_reg")] > ) > > (define_insn "*aarch64_sisd_neg_qi" > @@ -4961,8 +4960,7 @@ > UNSPEC_SISD_NEG))] > "TARGET_SIMD" > "neg\t%d0, %d1" > - [(set_attr "simd" "yes") > - (set_attr "type" "neon_neg")] > + [(set_attr "type" "neon_neg")] > ) > > ;; Rotate right > @@ -5598,9 +5596,8 @@ > "@ > <su_optab>cvtf\t%<GPF:s>0, %<s>1 > <su_optab>cvtf\t%<GPF:s>0, %<w1>1" > - [(set_attr "simd" "yes,no") > - (set_attr "fp" "no,yes") > - (set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f")] > + [(set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f") > + (set_attr "arch" "simd,fp")] > ) > > (define_insn "<optab><fcvt_iesize><GPF:mode>2" > @@ -5685,8 +5682,7 @@ > <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:w1>0, %<GPF:s>1, #%2 > <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:s>0, %<GPF:s>1, #%2" > [(set_attr "type" "f_cvtf2i, neon_fp_to_int_<GPF:Vetype>") > - (set_attr "fp" "yes, *") > - (set_attr "simd" "*, yes")] > + (set_attr "arch" "fp,simd")] > ) > > (define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3" > @@ -5699,8 +5695,7 @@ > <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:w>1, #%2 > <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:v>1, #%2" > [(set_attr "type" "f_cvti2f, neon_int_to_fp_<GPI:Vetype>") > - (set_attr "fp" "yes, *") > - (set_attr "simd" "*, yes")] > + (set_attr "arch" "fp,simd")] > ) > > (define_insn "<FCVT_F2FIXED:fcvt_fixed_insn>hf<mode>3" > > > use-arch-enabled-attribute.patch > > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index 5591c7b5a6bd7783c2b227add3e5a89d1a188f69..bea1c14e8ddabc4175be10790cd839c3a3852dab 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -1352,9 +1352,8 @@ > fmov\\t%d0, %1 > dup\\t%d0, %1" > [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*") > - (set_attr "length" "4")] > + (set_attr "length" "4") > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_insn "move_lo_quad_internal_<mode>" > @@ -1368,9 +1367,8 @@ > fmov\\t%d0, %1 > dup\\t%d0, %1" > [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*") > - (set_attr "length" "4")] > + (set_attr "length" "4") > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_insn "move_lo_quad_internal_be_<mode>" > @@ -1384,9 +1382,8 @@ > fmov\\t%d0, %1 > dup\\t%d0, %1" > [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*") > - (set_attr "length" "4")] > + (set_attr "length" "4") > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_insn "move_lo_quad_internal_be_<mode>" > @@ -1400,9 +1397,8 @@ > fmov\\t%d0, %1 > dup\\t%d0, %1" > [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*") > - (set_attr "length" "4")] > + (set_attr "length" "4") > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_expand "move_lo_quad_<mode>" > @@ -3114,8 +3110,7 @@ > fmov\t%d0, %1 > ldr\\t%d0, %1" > [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*")] > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_insn "*aarch64_combinez_be<mode>" > @@ -3129,8 +3124,7 @@ > fmov\t%d0, %1 > ldr\\t%d0, %1" > [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg") > - (set_attr "simd" "yes,*,yes") > - (set_attr "fp" "*,yes,*")] > + (set_attr "arch" "simd,fp,simd")] > ) > > (define_expand "aarch64_combine<mode>" > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 955bf1814b92d2bbf72d46bb2050998385174200..52ad814aafa8645342342cc6d67084af57e4b343 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -237,41 +237,51 @@ > ;; FP or SIMD registers then the pattern predicate should include TARGET_FLOAT > ;; or TARGET_SIMD. > > -;; Attribute that specifies whether or not the instruction touches fp > -;; registers. When this is set to yes for an alternative, that alternative > -;; will be disabled when !TARGET_FLOAT. > -(define_attr "fp" "no,yes" (const_string "no")) > +;; Attributes of the architecture required to support the instruction (or > +;; alternative). This attribute is used to compute attribute "enabled", use type > +;; "any" to enable an alternative in all cases. > > -;; Attribute that specifies whether or not the instruction touches half > -;; precision fp registers. When this is set to yes for an alternative, > -;; that alternative will be disabled when !TARGET_FP_F16INST. > -(define_attr "fp16" "no,yes" (const_string "no")) > +(define_enum "arches" [ any fp simd sve fp16]) > > -;; Attribute that specifies whether or not the instruction touches simd > -;; registers. When this is set to yes for an alternative, that alternative > -;; will be disabled when !TARGET_SIMD. > -(define_attr "simd" "no,yes" (const_string "no")) > +(define_enum_attr "arch" "arches" (const_string "any")) > > -;; Attribute that specifies whether or not the instruction uses SVE. > -;; When this is set to yes for an alternative, that alternative > -;; will be disabled when !TARGET_SVE. > -(define_attr "sve" "no,yes" (const_string "no")) > +;; [For compatibility with Arm in pipeline models] > +;; Attribute that specifies whether or not the instruction touches fp > +;; registers. > +;; Note that this attribute is not used anywhere in either the arm or aarch64 > +;; backends except in the scheduling description for xgene1. In that > +;; scheduling description this attribute is used to subclass the load_4 and > +;; load_8 types. > +(define_attr "fp" "no,yes" > + (if_then_else > + (eq_attr "arch" "fp") > + (const_string "yes") > + (const_string "no"))) > + > +(define_attr "arch_enabled" "no,yes" > + (if_then_else > + (ior > + (eq_attr "arch" "any") > + > + (and (eq_attr "arch" "fp") > + (match_test "TARGET_FLOAT")) > + > + (and (eq_attr "arch" "simd") > + (match_test "TARGET_SIMD")) > + > + (and (eq_attr "arch" "fp16") > + (match_test "TARGET_FP_F16INST")) > + > + (and (eq_attr "arch" "sve") > + (match_test "TARGET_SVE"))) > + (const_string "yes") > + (const_string "no"))) > > ;; Attribute that controls whether an alternative is enabled or not. > ;; Currently it is only used to disable alternatives which touch fp or simd > -;; registers when -mgeneral-regs-only is specified. > -(define_attr "enabled" "no,yes" > - (cond [(ior > - (and (eq_attr "fp" "yes") > - (eq (symbol_ref "TARGET_FLOAT") (const_int 0))) > - (and (eq_attr "simd" "yes") > - (eq (symbol_ref "TARGET_SIMD") (const_int 0))) > - (and (eq_attr "fp16" "yes") > - (eq (symbol_ref "TARGET_FP_F16INST") (const_int 0))) > - (and (eq_attr "sve" "yes") > - (eq (symbol_ref "TARGET_SVE") (const_int 0)))) > - (const_string "no") > - ] (const_string "yes"))) > +;; registers when -mgeneral-regs-only is specified or to require a special > +;; architecture support. > +(define_attr "enabled" "no,yes" (attr "arch_enabled")) > > ;; Attribute that specifies whether we are dealing with a branch to a > ;; label that is far away, i.e. further away than the maximum/minimum > @@ -987,8 +997,7 @@ > ;; The "mov_imm" type for CNT is just a placeholder. > [(set_attr "type" "mov_reg,mov_imm,neon_move,mov_imm,load_4,load_4,store_4, > store_4,neon_to_gp<q>,neon_from_gp<q>,neon_dup") > - (set_attr "simd" "*,*,yes,*,*,*,*,*,yes,yes,yes") > - (set_attr "sve" "*,*,*,yes,*,*,*,*,*,*,*")] > + (set_attr "arch" "*,*,simd,sve,*,*,*,*,simd,simd,simd")] > ) > > (define_expand "mov<mode>" > @@ -1047,9 +1056,7 @@ > ;; The "mov_imm" type for CNT is just a placeholder. > [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,load_4, > load_4,store_4,store_4,adr,adr,f_mcr,f_mrc,fmov,neon_move") > - (set_attr "fp" "*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") > - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") > - (set_attr "sve" "*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] > + (set_attr "arch" "*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] > ) > > (define_insn_and_split "*movdi_aarch64" > @@ -1086,9 +1093,7 @@ > [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,mov_imm, > load_8,load_8,store_8,store_8,adr,adr,f_mcr,f_mrc,fmov, > neon_move") > - (set_attr "fp" "*,*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") > - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") > - (set_attr "sve" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] > + (set_attr "arch" "*,*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] > ) > > (define_insn "insv_imm<mode>" > @@ -1141,8 +1146,7 @@ > load_16,store_16,store_16,\ > load_16,store_16") > (set_attr "length" "8,8,8,4,4,4,4,4,4") > - (set_attr "simd" "*,*,*,yes,*,*,*,*,*") > - (set_attr "fp" "*,*,*,*,*,*,*,yes,yes")] > + (set_attr "arch" "*,*,*,simd,*,*,*,fp,fp")] > ) > > ;; Split a TImode register-register or register-immediate move into > @@ -1196,8 +1200,7 @@ > mov\\t%w0, %w1" > [(set_attr "type" "neon_move,f_mcr,neon_move,neon_to_gp, neon_move,fconsts, \ > neon_move,f_loads,f_stores,load_4,store_4,mov_reg") > - (set_attr "simd" "yes,*,yes,yes,yes,*,yes,*,*,*,*,*") > - (set_attr "fp16" "*,yes,*,*,*,yes,*,*,*,*,*,*")] > + (set_attr "arch" "simd,fp16,simd,simd,simd,fp16,simd,*,*,*,*,*")] > ) > > (define_insn "*movsf_aarch64" > @@ -1221,7 +1224,7 @@ > [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,neon_move,\ > f_loads,f_stores,load_4,store_4,mov_reg,\ > fconsts") > - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] > + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] > ) > > (define_insn "*movdf_aarch64" > @@ -1245,7 +1248,7 @@ > [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,neon_move,\ > f_loadd,f_stored,load_8,store_8,mov_reg,\ > fconstd") > - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] > + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] > ) > > (define_split > @@ -1290,7 +1293,7 @@ > [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\ > f_loadd,f_stored,load_16,store_16,store_16") > (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4") > - (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")] > + (set_attr "arch" "simd,*,*,*,simd,*,*,*,*,*,*")] > ) > > (define_split > @@ -1337,7 +1340,7 @@ > ldp\\t%w0, %w2, %1 > ldp\\t%s0, %s2, %1" > [(set_attr "type" "load_8,neon_load1_2reg") > - (set_attr "fp" "*,yes")] > + (set_attr "arch" "*,fp")] > ) > > ;; Storing different modes that can still be merged > @@ -1354,7 +1357,7 @@ > ldp\\t%x0, %x2, %1 > ldp\\t%d0, %d2, %1" > [(set_attr "type" "load_16,neon_load1_2reg") > - (set_attr "fp" "*,yes")] > + (set_attr "arch" "*,fp")] > ) > > ;; Operands 0 and 2 are tied together by the final condition; so we allow > @@ -1372,7 +1375,7 @@ > stp\\t%w1, %w3, %0 > stp\\t%s1, %s3, %0" > [(set_attr "type" "store_8,neon_store1_2reg") > - (set_attr "fp" "*,yes")] > + (set_attr "arch" "*,fp")] > ) > > ;; Storing different modes that can still be merged > @@ -1389,7 +1392,7 @@ > stp\\t%x1, %x3, %0 > stp\\t%d1, %d3, %0" > [(set_attr "type" "store_16,neon_store1_2reg") > - (set_attr "fp" "*,yes")] > + (set_attr "arch" "*,fp")] > ) > > ;; Load pair with post-index writeback. This is primarily used in function > @@ -1615,7 +1618,7 @@ > * return aarch64_output_sve_addvl_addpl (operands[0], operands[1], operands[2]);" > ;; The "alu_imm" type for ADDVL/ADDPL is just a placeholder. > [(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm,multiple,alu_imm") > - (set_attr "simd" "*,*,yes,*,*,*")] > + (set_attr "arch" "*,*,simd,*,*,*")] > ) > > ;; zero_extend version of above > @@ -2618,7 +2621,7 @@ > sub\\t%x0, %x1, %x2 > sub\\t%d0, %d1, %d2" > [(set_attr "type" "alu_sreg, neon_sub") > - (set_attr "simd" "*,yes")] > + (set_attr "arch" "*,simd")] > ) > > (define_expand "subv<mode>4" > @@ -3225,7 +3228,7 @@ > neg\\t%<w>0, %<w>1 > neg\\t%<rtn>0<vas>, %<rtn>1<vas>" > [(set_attr "type" "alu_sreg, neon_neg<q>") > - (set_attr "simd" "*,yes")] > + (set_attr "arch" "*,simd")] > ) > > ;; zero_extend version of above > @@ -4070,7 +4073,7 @@ > <logical>\\t%<w>0, %<w>1, %2 > <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>" > [(set_attr "type" "logic_reg,logic_imm,neon_logic") > - (set_attr "simd" "*,*,yes")] > + (set_attr "arch" "*,*,simd")] > ) > > ;; zero_extend version of above > @@ -4204,7 +4207,7 @@ > mvn\\t%<w>0, %<w>1 > mvn\\t%0.8b, %1.8b" > [(set_attr "type" "logic_reg,neon_logic") > - (set_attr "simd" "*,yes")] > + (set_attr "arch" "*,simd")] > ) > > (define_insn "*one_cmpl_<optab><mode>2" > @@ -4227,7 +4230,7 @@ > <NLOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1 > <NLOGICAL:nlogical>\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>" > [(set_attr "type" "logic_reg,neon_logic") > - (set_attr "simd" "*,yes")] > + (set_attr "arch" "*,simd")] > ) > > (define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze" > @@ -4267,7 +4270,7 @@ > (set (match_dup 0) (not:GPI (match_dup 0)))] > "" > [(set_attr "type" "logic_reg,multiple") > - (set_attr "simd" "*,yes")] > + (set_attr "arch" "*,simd")] > ) > > (define_insn "*and_one_cmpl<mode>3_compare0" > @@ -4811,8 +4814,8 @@ > lsl\t%<w>0, %<w>1, %<w>2 > shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2 > ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>" > - [(set_attr "simd" "no,no,yes,yes") > - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")] > + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>") > + (set_attr "arch" "*,*,simd,simd")] > ) > > ;; Logical right shift using SISD or Integer instruction > @@ -4829,8 +4832,8 @@ > ushr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 > # > #" > - [(set_attr "simd" "no,no,yes,yes,yes") > - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] > + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>") > + (set_attr "arch" "*,*,simd,simd,simd")] > ) > > (define_split > @@ -4877,8 +4880,8 @@ > sshr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 > # > #" > - [(set_attr "simd" "no,no,yes,yes,yes") > - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] > + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>") > + (set_attr "arch" "*,*,simd,simd,simd")] > ) > > (define_split > @@ -4918,8 +4921,7 @@ > UNSPEC_SISD_USHL))] > "TARGET_SIMD" > "ushl\t%d0, %d1, %d2" > - [(set_attr "simd" "yes") > - (set_attr "type" "neon_shift_reg")] > + [(set_attr "type" "neon_shift_reg")] > ) > > (define_insn "*aarch64_ushl_2s" > @@ -4929,8 +4931,7 @@ > UNSPEC_USHL_2S))] > "TARGET_SIMD" > "ushl\t%0.2s, %1.2s, %2.2s" > - [(set_attr "simd" "yes") > - (set_attr "type" "neon_shift_reg")] > + [(set_attr "type" "neon_shift_reg")] > ) > > (define_insn "*aarch64_sisd_sshl" > @@ -4940,8 +4941,7 @@ > UNSPEC_SISD_SSHL))] > "TARGET_SIMD" > "sshl\t%d0, %d1, %d2" > - [(set_attr "simd" "yes") > - (set_attr "type" "neon_shift_reg")] > + [(set_attr "type" "neon_shift_reg")] > ) > > (define_insn "*aarch64_sshl_2s" > @@ -4951,8 +4951,7 @@ > UNSPEC_SSHL_2S))] > "TARGET_SIMD" > "sshl\t%0.2s, %1.2s, %2.2s" > - [(set_attr "simd" "yes") > - (set_attr "type" "neon_shift_reg")] > + [(set_attr "type" "neon_shift_reg")] > ) > > (define_insn "*aarch64_sisd_neg_qi" > @@ -4961,8 +4960,7 @@ > UNSPEC_SISD_NEG))] > "TARGET_SIMD" > "neg\t%d0, %d1" > - [(set_attr "simd" "yes") > - (set_attr "type" "neon_neg")] > + [(set_attr "type" "neon_neg")] > ) > > ;; Rotate right > @@ -5598,9 +5596,8 @@ > "@ > <su_optab>cvtf\t%<GPF:s>0, %<s>1 > <su_optab>cvtf\t%<GPF:s>0, %<w1>1" > - [(set_attr "simd" "yes,no") > - (set_attr "fp" "no,yes") > - (set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f")] > + [(set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f") > + (set_attr "arch" "simd,fp")] > ) > > (define_insn "<optab><fcvt_iesize><GPF:mode>2" > @@ -5685,8 +5682,7 @@ > <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:w1>0, %<GPF:s>1, #%2 > <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:s>0, %<GPF:s>1, #%2" > [(set_attr "type" "f_cvtf2i, neon_fp_to_int_<GPF:Vetype>") > - (set_attr "fp" "yes, *") > - (set_attr "simd" "*, yes")] > + (set_attr "arch" "fp,simd")] > ) > > (define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3" > @@ -5699,8 +5695,7 @@ > <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:w>1, #%2 > <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:v>1, #%2" > [(set_attr "type" "f_cvti2f, neon_int_to_fp_<GPI:Vetype>") > - (set_attr "fp" "yes, *") > - (set_attr "simd" "*, yes")] > + (set_attr "arch" "fp,simd")] > ) > > (define_insn "<FCVT_F2FIXED:fcvt_fixed_insn>hf<mode>3" >
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5591c7b5a6bd7783c2b227add3e5a89d1a188f69..bea1c14e8ddabc4175be10790cd839c3a3852dab 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1352,9 +1352,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_<mode>" @@ -1368,9 +1367,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_be_<mode>" @@ -1384,9 +1382,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_be_<mode>" @@ -1400,9 +1397,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_expand "move_lo_quad_<mode>" @@ -3114,8 +3110,7 @@ fmov\t%d0, %1 ldr\\t%d0, %1" [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*")] + (set_attr "arch" "simd,fp,simd")] ) (define_insn "*aarch64_combinez_be<mode>" @@ -3129,8 +3124,7 @@ fmov\t%d0, %1 ldr\\t%d0, %1" [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*")] + (set_attr "arch" "simd,fp,simd")] ) (define_expand "aarch64_combine<mode>" diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 955bf1814b92d2bbf72d46bb2050998385174200..52ad814aafa8645342342cc6d67084af57e4b343 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -237,41 +237,51 @@ ;; FP or SIMD registers then the pattern predicate should include TARGET_FLOAT ;; or TARGET_SIMD. -;; Attribute that specifies whether or not the instruction touches fp -;; registers. When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_FLOAT. -(define_attr "fp" "no,yes" (const_string "no")) +;; Attributes of the architecture required to support the instruction (or +;; alternative). This attribute is used to compute attribute "enabled", use type +;; "any" to enable an alternative in all cases. -;; Attribute that specifies whether or not the instruction touches half -;; precision fp registers. When this is set to yes for an alternative, -;; that alternative will be disabled when !TARGET_FP_F16INST. -(define_attr "fp16" "no,yes" (const_string "no")) +(define_enum "arches" [ any fp simd sve fp16]) -;; Attribute that specifies whether or not the instruction touches simd -;; registers. When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_SIMD. -(define_attr "simd" "no,yes" (const_string "no")) +(define_enum_attr "arch" "arches" (const_string "any")) -;; Attribute that specifies whether or not the instruction uses SVE. -;; When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_SVE. -(define_attr "sve" "no,yes" (const_string "no")) +;; [For compatibility with Arm in pipeline models] +;; Attribute that specifies whether or not the instruction touches fp +;; registers. +;; Note that this attribute is not used anywhere in either the arm or aarch64 +;; backends except in the scheduling description for xgene1. In that +;; scheduling description this attribute is used to subclass the load_4 and +;; load_8 types. +(define_attr "fp" "no,yes" + (if_then_else + (eq_attr "arch" "fp") + (const_string "yes") + (const_string "no"))) + +(define_attr "arch_enabled" "no,yes" + (if_then_else + (ior + (eq_attr "arch" "any") + + (and (eq_attr "arch" "fp") + (match_test "TARGET_FLOAT")) + + (and (eq_attr "arch" "simd") + (match_test "TARGET_SIMD")) + + (and (eq_attr "arch" "fp16") + (match_test "TARGET_FP_F16INST")) + + (and (eq_attr "arch" "sve") + (match_test "TARGET_SVE"))) + (const_string "yes") + (const_string "no"))) ;; Attribute that controls whether an alternative is enabled or not. ;; Currently it is only used to disable alternatives which touch fp or simd -;; registers when -mgeneral-regs-only is specified. -(define_attr "enabled" "no,yes" - (cond [(ior - (and (eq_attr "fp" "yes") - (eq (symbol_ref "TARGET_FLOAT") (const_int 0))) - (and (eq_attr "simd" "yes") - (eq (symbol_ref "TARGET_SIMD") (const_int 0))) - (and (eq_attr "fp16" "yes") - (eq (symbol_ref "TARGET_FP_F16INST") (const_int 0))) - (and (eq_attr "sve" "yes") - (eq (symbol_ref "TARGET_SVE") (const_int 0)))) - (const_string "no") - ] (const_string "yes"))) +;; registers when -mgeneral-regs-only is specified or to require a special +;; architecture support. +(define_attr "enabled" "no,yes" (attr "arch_enabled")) ;; Attribute that specifies whether we are dealing with a branch to a ;; label that is far away, i.e. further away than the maximum/minimum @@ -987,8 +997,7 @@ ;; The "mov_imm" type for CNT is just a placeholder. [(set_attr "type" "mov_reg,mov_imm,neon_move,mov_imm,load_4,load_4,store_4, store_4,neon_to_gp<q>,neon_from_gp<q>,neon_dup") - (set_attr "simd" "*,*,yes,*,*,*,*,*,yes,yes,yes") - (set_attr "sve" "*,*,*,yes,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,simd,sve,*,*,*,*,simd,simd,simd")] ) (define_expand "mov<mode>" @@ -1047,9 +1056,7 @@ ;; The "mov_imm" type for CNT is just a placeholder. [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,load_4, load_4,store_4,store_4,adr,adr,f_mcr,f_mrc,fmov,neon_move") - (set_attr "fp" "*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") - (set_attr "sve" "*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] ) (define_insn_and_split "*movdi_aarch64" @@ -1086,9 +1093,7 @@ [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,mov_imm, load_8,load_8,store_8,store_8,adr,adr,f_mcr,f_mrc,fmov, neon_move") - (set_attr "fp" "*,*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") - (set_attr "sve" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] ) (define_insn "insv_imm<mode>" @@ -1141,8 +1146,7 @@ load_16,store_16,store_16,\ load_16,store_16") (set_attr "length" "8,8,8,4,4,4,4,4,4") - (set_attr "simd" "*,*,*,yes,*,*,*,*,*") - (set_attr "fp" "*,*,*,*,*,*,*,yes,yes")] + (set_attr "arch" "*,*,*,simd,*,*,*,fp,fp")] ) ;; Split a TImode register-register or register-immediate move into @@ -1196,8 +1200,7 @@ mov\\t%w0, %w1" [(set_attr "type" "neon_move,f_mcr,neon_move,neon_to_gp, neon_move,fconsts, \ neon_move,f_loads,f_stores,load_4,store_4,mov_reg") - (set_attr "simd" "yes,*,yes,yes,yes,*,yes,*,*,*,*,*") - (set_attr "fp16" "*,yes,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,fp16,simd,simd,simd,fp16,simd,*,*,*,*,*")] ) (define_insn "*movsf_aarch64" @@ -1221,7 +1224,7 @@ [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,neon_move,\ f_loads,f_stores,load_4,store_4,mov_reg,\ fconsts") - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] ) (define_insn "*movdf_aarch64" @@ -1245,7 +1248,7 @@ [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,neon_move,\ f_loadd,f_stored,load_8,store_8,mov_reg,\ fconstd") - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] ) (define_split @@ -1290,7 +1293,7 @@ [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\ f_loadd,f_stored,load_16,store_16,store_16") (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4") - (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,simd,*,*,*,*,*,*")] ) (define_split @@ -1337,7 +1340,7 @@ ldp\\t%w0, %w2, %1 ldp\\t%s0, %s2, %1" [(set_attr "type" "load_8,neon_load1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Storing different modes that can still be merged @@ -1354,7 +1357,7 @@ ldp\\t%x0, %x2, %1 ldp\\t%d0, %d2, %1" [(set_attr "type" "load_16,neon_load1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Operands 0 and 2 are tied together by the final condition; so we allow @@ -1372,7 +1375,7 @@ stp\\t%w1, %w3, %0 stp\\t%s1, %s3, %0" [(set_attr "type" "store_8,neon_store1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Storing different modes that can still be merged @@ -1389,7 +1392,7 @@ stp\\t%x1, %x3, %0 stp\\t%d1, %d3, %0" [(set_attr "type" "store_16,neon_store1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Load pair with post-index writeback. This is primarily used in function @@ -1615,7 +1618,7 @@ * return aarch64_output_sve_addvl_addpl (operands[0], operands[1], operands[2]);" ;; The "alu_imm" type for ADDVL/ADDPL is just a placeholder. [(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm,multiple,alu_imm") - (set_attr "simd" "*,*,yes,*,*,*")] + (set_attr "arch" "*,*,simd,*,*,*")] ) ;; zero_extend version of above @@ -2618,7 +2621,7 @@ sub\\t%x0, %x1, %x2 sub\\t%d0, %d1, %d2" [(set_attr "type" "alu_sreg, neon_sub") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_expand "subv<mode>4" @@ -3225,7 +3228,7 @@ neg\\t%<w>0, %<w>1 neg\\t%<rtn>0<vas>, %<rtn>1<vas>" [(set_attr "type" "alu_sreg, neon_neg<q>") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) ;; zero_extend version of above @@ -4070,7 +4073,7 @@ <logical>\\t%<w>0, %<w>1, %2 <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>" [(set_attr "type" "logic_reg,logic_imm,neon_logic") - (set_attr "simd" "*,*,yes")] + (set_attr "arch" "*,*,simd")] ) ;; zero_extend version of above @@ -4204,7 +4207,7 @@ mvn\\t%<w>0, %<w>1 mvn\\t%0.8b, %1.8b" [(set_attr "type" "logic_reg,neon_logic") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*one_cmpl_<optab><mode>2" @@ -4227,7 +4230,7 @@ <NLOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1 <NLOGICAL:nlogical>\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>" [(set_attr "type" "logic_reg,neon_logic") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze" @@ -4267,7 +4270,7 @@ (set (match_dup 0) (not:GPI (match_dup 0)))] "" [(set_attr "type" "logic_reg,multiple") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*and_one_cmpl<mode>3_compare0" @@ -4811,8 +4814,8 @@ lsl\t%<w>0, %<w>1, %<w>2 shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2 ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>" - [(set_attr "simd" "no,no,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>") + (set_attr "arch" "*,*,simd,simd")] ) ;; Logical right shift using SISD or Integer instruction @@ -4829,8 +4832,8 @@ ushr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 # #" - [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>") + (set_attr "arch" "*,*,simd,simd,simd")] ) (define_split @@ -4877,8 +4880,8 @@ sshr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 # #" - [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>") + (set_attr "arch" "*,*,simd,simd,simd")] ) (define_split @@ -4918,8 +4921,7 @@ UNSPEC_SISD_USHL))] "TARGET_SIMD" "ushl\t%d0, %d1, %d2" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_ushl_2s" @@ -4929,8 +4931,7 @@ UNSPEC_USHL_2S))] "TARGET_SIMD" "ushl\t%0.2s, %1.2s, %2.2s" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sisd_sshl" @@ -4940,8 +4941,7 @@ UNSPEC_SISD_SSHL))] "TARGET_SIMD" "sshl\t%d0, %d1, %d2" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sshl_2s" @@ -4951,8 +4951,7 @@ UNSPEC_SSHL_2S))] "TARGET_SIMD" "sshl\t%0.2s, %1.2s, %2.2s" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sisd_neg_qi" @@ -4961,8 +4960,7 @@ UNSPEC_SISD_NEG))] "TARGET_SIMD" "neg\t%d0, %d1" - [(set_attr "simd" "yes") - (set_attr "type" "neon_neg")] + [(set_attr "type" "neon_neg")] ) ;; Rotate right @@ -5598,9 +5596,8 @@ "@ <su_optab>cvtf\t%<GPF:s>0, %<s>1 <su_optab>cvtf\t%<GPF:s>0, %<w1>1" - [(set_attr "simd" "yes,no") - (set_attr "fp" "no,yes") - (set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f")] + [(set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f") + (set_attr "arch" "simd,fp")] ) (define_insn "<optab><fcvt_iesize><GPF:mode>2" @@ -5685,8 +5682,7 @@ <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:w1>0, %<GPF:s>1, #%2 <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:s>0, %<GPF:s>1, #%2" [(set_attr "type" "f_cvtf2i, neon_fp_to_int_<GPF:Vetype>") - (set_attr "fp" "yes, *") - (set_attr "simd" "*, yes")] + (set_attr "arch" "fp,simd")] ) (define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3" @@ -5699,8 +5695,7 @@ <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:w>1, #%2 <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:v>1, #%2" [(set_attr "type" "f_cvti2f, neon_int_to_fp_<GPI:Vetype>") - (set_attr "fp" "yes, *") - (set_attr "simd" "*, yes")] + (set_attr "arch" "fp,simd")] ) (define_insn "<FCVT_F2FIXED:fcvt_fixed_insn>hf<mode>3"
Hello, arm.md has some attributes "arch" and "arch_enabled" to aid enabling and disabling insn alternatives based on the architecture being targeted. This patch introduces a similar attribute in the aarch64 backend. The new attribute will be used to enable a new alternative for the atomic_store insn in a future patch, but is an atomic change in itself. The new attribute has values "any", "fp", "fp16", "simd", and "sve". These attribute values have been taken from the pre-existing attributes "fp", "fp16", "simd", and "sve". The standalone "fp" attribute has been reintroduced in terms of the "arch" attribute as it's needed for the xgene1.md scheduling file -- the use in this file can't be changed to check for `(eq_attr "arch" "fp")` as the file is reused by the arm.md machine description whose 'arch' attribute doesn't have an 'fp' value. Full bootstrap and regression test done on aarch64. Ok for trunk? I don't have commit rights, so could someone commit it if accepted. gcc/ChangeLog: 2018-08-23 Matthew Malcomson <matthew.malcomson@arm.com> * config/aarch64/aarch64.md (arches): New enum. (arch): New enum attr. (arch_enabled): New attr. (enabled): Now uses arch_enabled only. (simd, sve, fp16): Removed attribute. (fp): Attr now defined in terms of 'arch'. (*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64, *movti_aarch64, *movhf_aarch64, <optab><fcvt_target><GPF:mode>2, <FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3, <FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3): Merge 'fp' and 'simd' attributes into 'arch'. (*movsf_aarch64, *movdf_aarch64, *movtf_aarch64, *add<mode>3_aarch64, subdi3, neg<mode>2, <optab><mode>3, one_cmpl<mode>2, *<NLOGICAL:optab>_one_cmpl<mode>3, *xor_one_cmpl<mode>3, *aarch64_ashl_sisd_or_int_<mode>3, *aarch64_lshr_sisd_or_int_<mode>3, *aarch64_ashr_sisd_or_int_<mode>3, *aarch64_sisd_ushl): Convert use of 'simd' attribute into 'arch'. (load_pair_sw_<SX:mode><SX2:mode>, load_pair_dw_<DX:mode><DX2:mode>, store_pair_sw_<SX:mode><SX2:mode>, store_pair_dw_<DX:mode><DX2:mode>): Convert use of 'fp' attribute to 'arch'. * config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>, move_lo_quad_internal_<mode>): (different modes) Merge 'fp' and 'simd' into 'arch'. (move_lo_quad_internal_be_<mode>, move_lo_quad_internal_be_<mode>): (different modes) Merge 'fp' and 'simd' into 'arch'. (*aarch64_combinez<mode>, *aarch64_combinez_be<mode>): Merge 'fp' and 'simd' into 'arch'. ############### Attachment also inlined for ease of reply ############### diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5591c7b5a6bd7783c2b227add3e5a89d1a188f69..bea1c14e8ddabc4175be10790cd839c3a3852dab 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1352,9 +1352,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_<mode>" @@ -1368,9 +1367,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_be_<mode>" @@ -1384,9 +1382,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_insn "move_lo_quad_internal_be_<mode>" @@ -1400,9 +1397,8 @@ fmov\\t%d0, %1 dup\\t%d0, %1" [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*") - (set_attr "length" "4")] + (set_attr "length" "4") + (set_attr "arch" "simd,fp,simd")] ) (define_expand "move_lo_quad_<mode>" @@ -3114,8 +3110,7 @@ fmov\t%d0, %1 ldr\\t%d0, %1" [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*")] + (set_attr "arch" "simd,fp,simd")] ) (define_insn "*aarch64_combinez_be<mode>" @@ -3129,8 +3124,7 @@ fmov\t%d0, %1 ldr\\t%d0, %1" [(set_attr "type" "neon_move<q>, neon_from_gp, neon_load1_1reg") - (set_attr "simd" "yes,*,yes") - (set_attr "fp" "*,yes,*")] + (set_attr "arch" "simd,fp,simd")] ) (define_expand "aarch64_combine<mode>" diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 955bf1814b92d2bbf72d46bb2050998385174200..52ad814aafa8645342342cc6d67084af57e4b343 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -237,41 +237,51 @@ ;; FP or SIMD registers then the pattern predicate should include TARGET_FLOAT ;; or TARGET_SIMD. -;; Attribute that specifies whether or not the instruction touches fp -;; registers. When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_FLOAT. -(define_attr "fp" "no,yes" (const_string "no")) +;; Attributes of the architecture required to support the instruction (or +;; alternative). This attribute is used to compute attribute "enabled", use type +;; "any" to enable an alternative in all cases. -;; Attribute that specifies whether or not the instruction touches half -;; precision fp registers. When this is set to yes for an alternative, -;; that alternative will be disabled when !TARGET_FP_F16INST. -(define_attr "fp16" "no,yes" (const_string "no")) +(define_enum "arches" [ any fp simd sve fp16]) -;; Attribute that specifies whether or not the instruction touches simd -;; registers. When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_SIMD. -(define_attr "simd" "no,yes" (const_string "no")) +(define_enum_attr "arch" "arches" (const_string "any")) -;; Attribute that specifies whether or not the instruction uses SVE. -;; When this is set to yes for an alternative, that alternative -;; will be disabled when !TARGET_SVE. -(define_attr "sve" "no,yes" (const_string "no")) +;; [For compatibility with Arm in pipeline models] +;; Attribute that specifies whether or not the instruction touches fp +;; registers. +;; Note that this attribute is not used anywhere in either the arm or aarch64 +;; backends except in the scheduling description for xgene1. In that +;; scheduling description this attribute is used to subclass the load_4 and +;; load_8 types. +(define_attr "fp" "no,yes" + (if_then_else + (eq_attr "arch" "fp") + (const_string "yes") + (const_string "no"))) + +(define_attr "arch_enabled" "no,yes" + (if_then_else + (ior + (eq_attr "arch" "any") + + (and (eq_attr "arch" "fp") + (match_test "TARGET_FLOAT")) + + (and (eq_attr "arch" "simd") + (match_test "TARGET_SIMD")) + + (and (eq_attr "arch" "fp16") + (match_test "TARGET_FP_F16INST")) + + (and (eq_attr "arch" "sve") + (match_test "TARGET_SVE"))) + (const_string "yes") + (const_string "no"))) ;; Attribute that controls whether an alternative is enabled or not. ;; Currently it is only used to disable alternatives which touch fp or simd -;; registers when -mgeneral-regs-only is specified. -(define_attr "enabled" "no,yes" - (cond [(ior - (and (eq_attr "fp" "yes") - (eq (symbol_ref "TARGET_FLOAT") (const_int 0))) - (and (eq_attr "simd" "yes") - (eq (symbol_ref "TARGET_SIMD") (const_int 0))) - (and (eq_attr "fp16" "yes") - (eq (symbol_ref "TARGET_FP_F16INST") (const_int 0))) - (and (eq_attr "sve" "yes") - (eq (symbol_ref "TARGET_SVE") (const_int 0)))) - (const_string "no") - ] (const_string "yes"))) +;; registers when -mgeneral-regs-only is specified or to require a special +;; architecture support. +(define_attr "enabled" "no,yes" (attr "arch_enabled")) ;; Attribute that specifies whether we are dealing with a branch to a ;; label that is far away, i.e. further away than the maximum/minimum @@ -987,8 +997,7 @@ ;; The "mov_imm" type for CNT is just a placeholder. [(set_attr "type" "mov_reg,mov_imm,neon_move,mov_imm,load_4,load_4,store_4, store_4,neon_to_gp<q>,neon_from_gp<q>,neon_dup") - (set_attr "simd" "*,*,yes,*,*,*,*,*,yes,yes,yes") - (set_attr "sve" "*,*,*,yes,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,simd,sve,*,*,*,*,simd,simd,simd")] ) (define_expand "mov<mode>" @@ -1047,9 +1056,7 @@ ;; The "mov_imm" type for CNT is just a placeholder. [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,load_4, load_4,store_4,store_4,adr,adr,f_mcr,f_mrc,fmov,neon_move") - (set_attr "fp" "*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") - (set_attr "sve" "*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] ) (define_insn_and_split "*movdi_aarch64" @@ -1086,9 +1093,7 @@ [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,mov_imm, load_8,load_8,store_8,store_8,adr,adr,f_mcr,f_mrc,fmov, neon_move") - (set_attr "fp" "*,*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") - (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes") - (set_attr "sve" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,*,*,*")] + (set_attr "arch" "*,*,*,*,*,*,sve,*,fp,*,fp,*,*,fp,fp,fp,simd")] ) (define_insn "insv_imm<mode>" @@ -1141,8 +1146,7 @@ load_16,store_16,store_16,\ load_16,store_16") (set_attr "length" "8,8,8,4,4,4,4,4,4") - (set_attr "simd" "*,*,*,yes,*,*,*,*,*") - (set_attr "fp" "*,*,*,*,*,*,*,yes,yes")] + (set_attr "arch" "*,*,*,simd,*,*,*,fp,fp")] ) ;; Split a TImode register-register or register-immediate move into @@ -1196,8 +1200,7 @@ mov\\t%w0, %w1" [(set_attr "type" "neon_move,f_mcr,neon_move,neon_to_gp, neon_move,fconsts, \ neon_move,f_loads,f_stores,load_4,store_4,mov_reg") - (set_attr "simd" "yes,*,yes,yes,yes,*,yes,*,*,*,*,*") - (set_attr "fp16" "*,yes,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,fp16,simd,simd,simd,fp16,simd,*,*,*,*,*")] ) (define_insn "*movsf_aarch64" @@ -1221,7 +1224,7 @@ [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,neon_move,\ f_loads,f_stores,load_4,store_4,mov_reg,\ fconsts") - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] ) (define_insn "*movdf_aarch64" @@ -1245,7 +1248,7 @@ [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,neon_move,\ f_loadd,f_stored,load_8,store_8,mov_reg,\ fconstd") - (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,*,simd,*,*,*,*,*,*")] ) (define_split @@ -1290,7 +1293,7 @@ [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\ f_loadd,f_stored,load_16,store_16,store_16") (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4") - (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")] + (set_attr "arch" "simd,*,*,*,simd,*,*,*,*,*,*")] ) (define_split @@ -1337,7 +1340,7 @@ ldp\\t%w0, %w2, %1 ldp\\t%s0, %s2, %1" [(set_attr "type" "load_8,neon_load1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Storing different modes that can still be merged @@ -1354,7 +1357,7 @@ ldp\\t%x0, %x2, %1 ldp\\t%d0, %d2, %1" [(set_attr "type" "load_16,neon_load1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Operands 0 and 2 are tied together by the final condition; so we allow @@ -1372,7 +1375,7 @@ stp\\t%w1, %w3, %0 stp\\t%s1, %s3, %0" [(set_attr "type" "store_8,neon_store1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Storing different modes that can still be merged @@ -1389,7 +1392,7 @@ stp\\t%x1, %x3, %0 stp\\t%d1, %d3, %0" [(set_attr "type" "store_16,neon_store1_2reg") - (set_attr "fp" "*,yes")] + (set_attr "arch" "*,fp")] ) ;; Load pair with post-index writeback. This is primarily used in function @@ -1615,7 +1618,7 @@ * return aarch64_output_sve_addvl_addpl (operands[0], operands[1], operands[2]);" ;; The "alu_imm" type for ADDVL/ADDPL is just a placeholder. [(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm,multiple,alu_imm") - (set_attr "simd" "*,*,yes,*,*,*")] + (set_attr "arch" "*,*,simd,*,*,*")] ) ;; zero_extend version of above @@ -2618,7 +2621,7 @@ sub\\t%x0, %x1, %x2 sub\\t%d0, %d1, %d2" [(set_attr "type" "alu_sreg, neon_sub") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_expand "subv<mode>4" @@ -3225,7 +3228,7 @@ neg\\t%<w>0, %<w>1 neg\\t%<rtn>0<vas>, %<rtn>1<vas>" [(set_attr "type" "alu_sreg, neon_neg<q>") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) ;; zero_extend version of above @@ -4070,7 +4073,7 @@ <logical>\\t%<w>0, %<w>1, %2 <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>" [(set_attr "type" "logic_reg,logic_imm,neon_logic") - (set_attr "simd" "*,*,yes")] + (set_attr "arch" "*,*,simd")] ) ;; zero_extend version of above @@ -4204,7 +4207,7 @@ mvn\\t%<w>0, %<w>1 mvn\\t%0.8b, %1.8b" [(set_attr "type" "logic_reg,neon_logic") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*one_cmpl_<optab><mode>2" @@ -4227,7 +4230,7 @@ <NLOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1 <NLOGICAL:nlogical>\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>" [(set_attr "type" "logic_reg,neon_logic") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze" @@ -4267,7 +4270,7 @@ (set (match_dup 0) (not:GPI (match_dup 0)))] "" [(set_attr "type" "logic_reg,multiple") - (set_attr "simd" "*,yes")] + (set_attr "arch" "*,simd")] ) (define_insn "*and_one_cmpl<mode>3_compare0" @@ -4811,8 +4814,8 @@ lsl\t%<w>0, %<w>1, %<w>2 shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2 ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>" - [(set_attr "simd" "no,no,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>") + (set_attr "arch" "*,*,simd,simd")] ) ;; Logical right shift using SISD or Integer instruction @@ -4829,8 +4832,8 @@ ushr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 # #" - [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>") + (set_attr "arch" "*,*,simd,simd,simd")] ) (define_split @@ -4877,8 +4880,8 @@ sshr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 # #" - [(set_attr "simd" "no,no,yes,yes,yes") - (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] + [(set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>") + (set_attr "arch" "*,*,simd,simd,simd")] ) (define_split @@ -4918,8 +4921,7 @@ UNSPEC_SISD_USHL))] "TARGET_SIMD" "ushl\t%d0, %d1, %d2" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_ushl_2s" @@ -4929,8 +4931,7 @@ UNSPEC_USHL_2S))] "TARGET_SIMD" "ushl\t%0.2s, %1.2s, %2.2s" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sisd_sshl" @@ -4940,8 +4941,7 @@ UNSPEC_SISD_SSHL))] "TARGET_SIMD" "sshl\t%d0, %d1, %d2" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sshl_2s" @@ -4951,8 +4951,7 @@ UNSPEC_SSHL_2S))] "TARGET_SIMD" "sshl\t%0.2s, %1.2s, %2.2s" - [(set_attr "simd" "yes") - (set_attr "type" "neon_shift_reg")] + [(set_attr "type" "neon_shift_reg")] ) (define_insn "*aarch64_sisd_neg_qi" @@ -4961,8 +4960,7 @@ UNSPEC_SISD_NEG))] "TARGET_SIMD" "neg\t%d0, %d1" - [(set_attr "simd" "yes") - (set_attr "type" "neon_neg")] + [(set_attr "type" "neon_neg")] ) ;; Rotate right @@ -5598,9 +5596,8 @@ "@ <su_optab>cvtf\t%<GPF:s>0, %<s>1 <su_optab>cvtf\t%<GPF:s>0, %<w1>1" - [(set_attr "simd" "yes,no") - (set_attr "fp" "no,yes") - (set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f")] + [(set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f") + (set_attr "arch" "simd,fp")] ) (define_insn "<optab><fcvt_iesize><GPF:mode>2" @@ -5685,8 +5682,7 @@ <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:w1>0, %<GPF:s>1, #%2 <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:s>0, %<GPF:s>1, #%2" [(set_attr "type" "f_cvtf2i, neon_fp_to_int_<GPF:Vetype>") - (set_attr "fp" "yes, *") - (set_attr "simd" "*, yes")] + (set_attr "arch" "fp,simd")] ) (define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3" @@ -5699,8 +5695,7 @@ <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:w>1, #%2 <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:v>1, #%2" [(set_attr "type" "f_cvti2f, neon_int_to_fp_<GPI:Vetype>") - (set_attr "fp" "yes, *") - (set_attr "simd" "*, yes")] + (set_attr "arch" "fp,simd")] ) (define_insn "<FCVT_F2FIXED:fcvt_fixed_insn>hf<mode>3"