From patchwork Sat Jan 22 00:37:51 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 79969 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id A18F7B70EB for ; Sat, 22 Jan 2011 11:38:13 +1100 (EST) Received: (qmail 8578 invoked by alias); 22 Jan 2011 00:38:11 -0000 Received: (qmail 8564 invoked by uid 22791); 22 Jan 2011 00:38:10 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RFC_ABUSE_POST, TW_IV X-Spam-Check-By: sourceware.org Received: from mail-fx0-f47.google.com (HELO mail-fx0-f47.google.com) (209.85.161.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 22 Jan 2011 00:37:55 +0000 Received: by fxm17 with SMTP id 17so2397925fxm.20 for ; Fri, 21 Jan 2011 16:37:53 -0800 (PST) MIME-Version: 1.0 Received: by 10.223.95.203 with SMTP id e11mr1341714fan.60.1295656671511; Fri, 21 Jan 2011 16:37:51 -0800 (PST) Received: by 10.223.70.129 with HTTP; Fri, 21 Jan 2011 16:37:51 -0800 (PST) Date: Sat, 22 Jan 2011 00:37:51 +0000 Message-ID: Subject: [RFC ARM] Fix PR43721 - combine multiple div and mod into a single divmod call. From: Ramana Radhakrishnan To: gcc-patches Cc: Richard Earnshaw X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, Though I don't claim to like this patch very much it seems to be the (cough) "standard" way for backends to get the single divmodsi4 library call generated rather than writing a separate pass to detect this . There has been some discussion about this with respect to the audit trail for http://gcc.gnu.org/PR23726 but that talks about writing a new pass to detect this or enhancing CSE to deal with multiple SETs across presumably various rtl insns. Ok to commit to trunk when stage1 opens and if tests show no regressions ? Any other comments with respect to this would be more than welcome. Ramana 2011-01-21 Ramana Radhakrishnan PR target/43721 gcc/ * config/arm/arm.md (divmodsi4): New. (aeabi_divmodsi4_call): New. (aeabi_divsi3_call): New. (udivmodsi4): Likewise. (aeabi_udivmodsi4_call): New. (aeabi_udivsi3_call): New. === modified file 'gcc/config/arm/arm.md' --- gcc/config/arm/arm.md 2011-01-13 16:06:19 +0000 +++ gcc/config/arm/arm.md 2011-01-21 17:34:35 +0000 @@ -11554,6 +11554,103 @@ " ) +(define_insn_and_split "divmodsi4" + [(parallel [(set (match_operand:SI 0 "s_register_operand" "") + (div:SI (match_operand:SI 1 "s_register_operand" "") + (match_operand:SI 2 "s_register_operand" ""))) + (set (match_operand:SI 3 "s_register_operand" "") + (mod:SI (match_dup 1) (match_dup 2))) + (clobber (reg:SI 0)) + (clobber (reg:SI 1)) + (clobber (reg:SI LR_REGNUM))])] + "" + "#" + "!(TARGET_THUMB2 && arm_arch_hwdiv)" + [(const_int 0)] + "{ + rtx r0_reg = gen_rtx_REG (SImode, 0); + rtx r1_reg = gen_rtx_REG (SImode, 1); + emit_move_insn (r0_reg, operands[1]); + emit_move_insn (r1_reg, operands[2]); + if (find_reg_note (curr_insn, REG_UNUSED, operands[3])) + /* This is only a call for div. */ + emit_insn (gen_aeabi_divsi3_call ()); + else + { + emit_insn (gen_aeabi_divmodsi4_call ()); + emit_move_insn (operands[3], r1_reg); + } + emit_move_insn (operands[0], r0_reg); + DONE; + } + ") + +(define_insn "aeabi_divmodsi4_call" + [(set (reg:SI 0) (div:SI (reg:SI 0) (reg:SI 1))) + (set (reg:SI 1) (mod:SI (reg:SI 0) (reg:SI 1))) + (clobber (reg:SI LR_REGNUM))] + "!(TARGET_THUMB2 && arm_arch_hwdiv)" + "bl\t__aeabi_idivmod" + [(set_attr "type" "call") + (set_attr "conds" "clob")]) + +(define_insn "aeabi_divsi3_call" + [(set (reg:SI 0) (div:SI (reg:SI 0) (reg:SI 1))) + (clobber (reg:SI LR_REGNUM))] + "!(TARGET_THUMB2 && arm_arch_hwdiv)" + "bl\t__aeabi_idiv" + [(set_attr "type" "call") + (set_attr "conds" "clob")]) + + +(define_insn_and_split "udivmodsi4" + [(parallel [(set (match_operand:SI 0 "s_register_operand" "") + (udiv:SI (match_operand:SI 1 "s_register_operand" "") + (match_operand:SI 2 "s_register_operand" ""))) + (set (match_operand:SI 3 "s_register_operand" "") + (umod:SI (match_dup 1) (match_dup 2))) + (clobber (reg:SI 0)) + (clobber (reg:SI 1)) + (clobber (reg:SI LR_REGNUM))])] + "" + "#" + "!(TARGET_THUMB2 && arm_arch_hwdiv)" + [(const_int 0)] + "{ + rtx r0_reg = gen_rtx_REG (SImode, 0); + rtx r1_reg = gen_rtx_REG (SImode, 1); + emit_move_insn (r0_reg, operands[1]); + emit_move_insn (r1_reg, operands[2]); + if (find_reg_note (curr_insn, REG_UNUSED, operands[3])) + /* This is only a call for div. */ + emit_insn (gen_aeabi_udivsi3_call ()); + else + { + emit_insn (gen_aeabi_udivmodsi4_call ()); + emit_move_insn (operands[3], r1_reg); + } + emit_move_insn (operands[0], r0_reg); + DONE; + } + ") + +(define_insn "aeabi_udivmodsi4_call" + [(set (reg:SI 0) (udiv:SI (reg:SI 0) (reg:SI 1))) + (set (reg:SI 1) (umod:SI (reg:SI 0) (reg:SI 1))) + (clobber (reg:SI LR_REGNUM))] + "!(TARGET_THUMB2 && arm_arch_hwdiv)" + "bl\t__aeabi_uidivmod" + [(set_attr "type" "call") + (set_attr "conds" "clob")]) + +(define_insn "aeabi_udivsi3_call" + [(set (reg:SI 0) (udiv:SI (reg:SI 0) (reg:SI 1))) + (clobber (reg:SI LR_REGNUM))] + "!(TARGET_THUMB2 && arm_arch_hwdiv)" + "bl\t__aeabi_uidiv" + [(set_attr "type" "call") + (set_attr "conds" "clob")]) + ;; Load the FPA co-processor patterns (include "fpa.md") ;; Load the Maverick co-processor patterns