diff mbox

[vect,loongson] make vect test available for loongson

Message ID AANLkTikC2oStkDpAiPVWl1GsodWOAXHrjJT41il8Bzu0@mail.gmail.com
State New
Headers show

Commit Message

Eric Fisher July 6, 2010, 9:06 a.m. UTC 
Hi,

This patch will modify the target-support.exp to enable vect_int,
vect_shift, vect_no_int_max, and vect_no_align for loongson target. So
that the auto-vectorization tests will be done.

Here's the test result when apply the early patch
(http://gcc.gnu.org/ml/gcc-patches/2010-07/msg00357.html) on trunk:

		=== gcc Summary ===

# of expected passes		55
# of unexpected failures	1
# of expected failures		6
# of unsupported tests		488
/home/xmj/tools/build-trunk/gcc/xgcc  version 4.6.0 20100706
(experimental) (GCC)

Here's the test result when apply this patch too:

		=== gcc Summary ===

# of expected passes		1020
# of unexpected failures	9
# of unexpected successes	15
# of expected failures		91
# of unsupported tests		141
/home/xmj/tools/build-trunk/gcc/xgcc  version 4.6.0 20100706
(experimental) (GCC)

The tests are run using cross compiler plus ssh, compile on ia64, run
on loongson2f.

ChangeLog

* target-supports.exp: enable vect_int, vect_shift, vect_no_int_max,
and vect_no_align for loongson target.

Thanks,
Eric
diff mbox

Patch

Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp	(revision 161865)
+++ gcc/testsuite/lib/target-supports.exp	(working copy)
@@ -1493,7 +1493,8 @@  proc check_effective_target_vect_int { }
 	      || [istarget sparc*-*-*]
 	      || [istarget alpha*-*-*]
 	      || [istarget ia64-*-*] 
-	      || [check_effective_target_arm32] } {
+	      || [check_effective_target_arm32]
+              || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_int_saved 1
 	}
     }
@@ -2029,7 +2030,8 @@  proc check_effective_target_vect_shift {
 	     || [istarget ia64-*-*]
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
-	     || [check_effective_target_arm32] } {
+	     || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_shift_saved 1
 	}
     }
@@ -2143,7 +2145,8 @@  proc check_effective_target_vect_no_int_
 	set et_vect_no_int_max_saved 0
 	if { [istarget sparc*-*-*]
 	     || [istarget spu-*-*]
-	     || [istarget alpha*-*-*] } {
+	     || [istarget alpha*-*-*]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_int_max_saved 1
 	}
     }
@@ -2516,7 +2519,8 @@  proc check_effective_target_vect_no_alig
 	if { [istarget mipsisa64*-*-*]
 	     || [istarget sparc*-*-*]
 	     || [istarget ia64-*-*]
-	     || [check_effective_target_arm32] } { 
+	     || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_align_saved 1
 	}
     }