From patchwork Fri Sep 27 02:33:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kewen.Lin" X-Patchwork-Id: 1168219 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-509684-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="VUP6k1v7"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46fbSg6wTnz9sPS for ; Fri, 27 Sep 2019 12:33:22 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:date:mime-version:content-type:message-id; q=dns; s=default; b=DZZer+a7bDya7LfRh7AX/park9ICUwzeKqimgu9KZW9Hn5KcrS nkkeZuIFb1DZuvor8Aq5kElz4h5MDOiZStwZXBFg/G/m8rkIbUZA+gk+3w0V9vV6 Fnf4YEqJa9jlM1fqed1BJfzQsyJAQzigSyVGQ5zQVPeg6i+wZBoAMeIQM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:date:mime-version:content-type:message-id; s= default; bh=OK0irbUN88LtvKf+K7ifoB5ajb0=; b=VUP6k1v7SLzVFbwscOQ6 /CMqpKjKsn2VM67+O0R2R1GqwEsulngX36U4kM91nSM4oHfo8zrA0NwXcFZS/aWq VTdd8OrtSt6lmxo2PiHHiV1JQGDjS9jgnoc3Yl02TgtilKFDQAs1D9TEf0/Mvty0 99OlEnym1ko9O67F9Hm2udM= Received: (qmail 52687 invoked by alias); 27 Sep 2019 02:33:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 52664 invoked by uid 89); 27 Sep 2019 02:33:13 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy=lin X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Sep 2019 02:33:12 +0000 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x8R2WI0s066222 for ; Thu, 26 Sep 2019 22:33:11 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2v998p8qst-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 26 Sep 2019 22:33:10 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 27 Sep 2019 03:33:06 +0100 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x8R2X4jB48627736 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 27 Sep 2019 02:33:04 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7104E4204B; Fri, 27 Sep 2019 02:33:04 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EE08442041; Fri, 27 Sep 2019 02:33:02 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.146.223]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 27 Sep 2019 02:33:02 +0000 (GMT) To: GCC Patches Cc: Segher Boessenkool , Bill Schmidt From: "Kewen.Lin" Subject: [PATCH, rs6000] Support float from/to long conversion vectorization Date: Fri, 27 Sep 2019 10:33:01 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 x-cbid: 19092702-4275-0000-0000-0000036BA08E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19092702-4276-0000-0000-0000387E20DE Message-Id: <9ec0e958-5efc-9395-8138-4b3109367379@linux.ibm.com> X-IsSubscribed: yes Hi, This patch is to add the support for float from/to long conversion vectorization. ISA 2.06 supports the vector version instructions for conversion between float and long long (both signed and unsigned), but vectorizer can't exploit them since the optab check fails. So this patch is mainly to add related optab supports. I've verified the functionality on both LE and BE. Bootstrapped and regress tested on powerpc64le-linux-gnu. Thanks, Kewen --- gcc/ChangeLog 2019-09-27 Kewen Lin * config/rs6000/vsx.md (vec_pack[su]_float_v2di): New define_expand. (vec_unpack_[su]fix_trunc_hi_v4sf): Likewise. (vec_unpack_[su]fix_trunc_lo_v4sf): Likewise. gcc/testsuite/ChangeLog 2019-09-27 Kewen Lin * gcc.target/powerpc/conv-vectorize-1.c: New test. * gcc.target/powerpc/conv-vectorize-2.c: New test. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 7633171..ef32971 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5538,3 +5538,42 @@ operands[SFBOOL_TMP_VSX_DI] = gen_rtx_REG (DImode, regno_tmp_vsx); operands[SFBOOL_MTVSR_D_V4SF] = gen_rtx_REG (V4SFmode, regno_mtvsr_d); }) + +;; Support signed/unsigned long long to float conversion vectorization. +(define_expand "vec_pack_float_v2di" + [(match_operand:V4SF 0 "vfloat_operand") + (any_float:V4SF (parallel [(match_operand:V2DI 1 "vint_operand") + (match_operand:V2DI 2 "vint_operand")]))] + "TARGET_VSX" +{ + rtx r1 = gen_reg_rtx (V4SFmode); + rtx r2 = gen_reg_rtx (V4SFmode); + emit_insn (gen_vsx_xvcvxdsp (r1, operands[1])); + emit_insn (gen_vsx_xvcvxdsp (r2, operands[2])); + rs6000_expand_extract_even (operands[0], r1, r2); + DONE; +}) + +;; Support float to signed/unsigned long long conversion vectorization. +(define_expand "vec_unpack_fix_trunc_hi_v4sf" + [(match_operand:V2DI 0 "vint_operand") + (any_fix:V2DI (match_operand:V4SF 1 "vfloat_operand"))] + "TARGET_VSX" +{ + rtx reg = gen_reg_rtx (V4SFmode); + rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); + emit_insn (gen_vsx_xvcvspxds (operands[0], reg)); + DONE; +}) + +(define_expand "vec_unpack_fix_trunc_lo_v4sf" + [(match_operand:V2DI 0 "vint_operand") + (any_fix:V2DI (match_operand:V4SF 1 "vfloat_operand"))] + "TARGET_VSX" +{ + rtx reg = gen_reg_rtx (V4SFmode); + rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); + emit_insn (gen_vsx_xvcvspxds (operands[0], reg)); + DONE; +}) + diff --git a/gcc/testsuite/gcc.target/powerpc/conv-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/conv-vectorize-1.c new file mode 100644 index 0000000..d96db14 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/conv-vectorize-1.c @@ -0,0 +1,37 @@ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mvsx" } */ + +/* Test vectorizer can exploit vector conversion instructions to convert + unsigned/signed long long to float. */ + +#include + +#define SIZE 32 +#define ALIGN 16 + +float sflt_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); +float uflt_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); + +unsigned long long ulong_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); +signed long long slong_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); + +void +convert_slong_to_float (void) +{ + size_t i; + + for (i = 0; i < SIZE; i++) + sflt_array[i] = (float) slong_array[i]; +} + +void +convert_ulong_to_float (void) +{ + size_t i; + + for (i = 0; i < SIZE; i++) + uflt_array[i] = (float) ulong_array[i]; +} + +/* { dg-final { scan-assembler {\mxvcvsxdsp\M} } } */ +/* { dg-final { scan-assembler {\mxvcvuxdsp\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/conv-vectorize-2.c b/gcc/testsuite/gcc.target/powerpc/conv-vectorize-2.c new file mode 100644 index 0000000..5dd5dea --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/conv-vectorize-2.c @@ -0,0 +1,37 @@ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mvsx" } */ + +/* Test vectorizer can exploit vector conversion instructions to convert + float to unsigned/signed long long. */ + +#include + +#define SIZE 32 +#define ALIGN 16 + +float sflt_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); +float uflt_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); + +unsigned long long ulong_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); +signed long long slong_array[SIZE] __attribute__ ((__aligned__ (ALIGN))); + +void +convert_float_to_slong (void) +{ + size_t i; + + for (i = 0; i < SIZE; i++) + slong_array[i] = (signed long long) sflt_array[i]; +} + +void +convert_float_to_ulong (void) +{ + size_t i; + + for (i = 0; i < SIZE; i++) + ulong_array[i] = (unsigned long long) uflt_array[i]; +} + +/* { dg-final { scan-assembler {\mxvcvspsxds\M} } } */ +/* { dg-final { scan-assembler {\mxvcvspuxds\M} } } */