From patchwork Wed Jul 4 01:05:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 939046 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-480975-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="W2SQxs3G"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41L2pk47nmz9s4c for ; Wed, 4 Jul 2018 11:05:15 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:message-id:date:mime-version:content-type; q=dns; s= default; b=SBwIuyDkrDRrmG+3PYlrS+EI+Z2t+oshXg1Dni9RI7aFTWmobJLqv O/UZgYlhxWar5dhBsSeE7VF7mH1znluslpX3GGIshv6OOPLHp2+GTnZX3VgxsHJC S0j1nL7mPWGIhMse23r1HOSeVt+2TUCeYBk/Z9olvwy2AR3WayMCXI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:message-id:date:mime-version:content-type; s= default; bh=sGVSdCT2bwMA7KbFlcrLyCofpaI=; b=W2SQxs3GTrzM88hqgLOh h1B41DG+eiqbktrVGOrzHhtO6LlLgHQRa7wYnp/BM5BqFQeP/XM+JRf7wRuzsTiL KH7ahMv9xI76dqiTQqMfTlCIvH8M7mHgfFDXB7eQKS5Xj39xotcjhn+RA1Ev0bPp smJYDOo7bQkMC80B3fk+Q3s= Received: (qmail 38101 invoked by alias); 4 Jul 2018 01:05:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 38084 invoked by uid 89); 4 Jul 2018 01:05:07 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_NUMSUBJECT, SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=ur X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 04 Jul 2018 01:05:05 +0000 Received: from smtp.corp.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 9110530832DD for ; Wed, 4 Jul 2018 01:05:04 +0000 (UTC) Received: from localhost.localdomain (ovpn-112-54.rdu2.redhat.com [10.10.112.54]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9EAD3D717E for ; Wed, 4 Jul 2018 01:05:03 +0000 (UTC) From: Jeff Law Openpgp: preference=signencrypt To: gcc-patches Subject: [committed] Consolidate xor/ior patterns and splitters for H8 Message-ID: <99d16790-7341-73bb-fa9b-23e264ef647b@redhat.com> Date: Tue, 3 Jul 2018 19:05:02 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 X-IsSubscribed: yes This patch consolidates the ior/xor expanders, patterns and splitters using a code iterator. This does make us a bit more lenient on what we accept for xor operands than we were before. However, AFAICT xor should accept the same operands as ior on all the supported H8 variants. The additional leniency in accepted operands for xor does result in improved code generation in some circumstances. For example, instead of something like this: ! 22c: 6e 7a 00 11 mov.b @(0x11:16,er7),r2l ! 230: 71 0a bnot #0x0,r2l ! 232: 6e fa 00 11 mov.b r2l,@(0x11:16,er7) Instead we get: ! 22c: 01 74 6e 78 xor.b #0x1,@(0x11:16,er7) ! 230: 00 11 d0 01 Shorter and saves a register. More importantly there's simply going to be fewer patterns & splitters to adjust for the transition away from cc0. Installed on the trunk. Jeff * config/h8300/h8300.md (ors code_iterator): New. (bsetqi_msx, bnotqi_msx patterns and splitters): Consolidate into a single pattern and single splitter. (bsethi_msx, bnothi_msx patterns): Consolidate into a single pattern. (iorqi3_1, xorqi3_1): Likewise. (iorqi3, xorqi3 expanders): Similarly. diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index e654784..f3cf421 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -193,6 +193,8 @@ (define_mode_iterator QHSIF [QI HI SI SF]) (define_code_iterator shifts [ashift ashiftrt lshiftrt]) + +(define_code_iterator ors [ior xor]) ;; ---------------------------------------------------------------------- ;; MOVE INSTRUCTIONS @@ -1597,126 +1599,44 @@ [(set_attr "length" "2")]) ;; ---------------------------------------------------------------------- -;; OR INSTRUCTIONS +;; OR/XOR INSTRUCTIONS ;; ---------------------------------------------------------------------- -(define_insn "bsetqi_msx" +(define_insn "bqi_msx" [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU") - (ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0") + (ors:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0") (match_operand:QI 2 "single_one_operand" "Y2")))] "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])" - "bset\\t%V2,%0" + { return == IOR ? "bset\\t%V2,%0" : "bnot\\t%V2,%0"; } [(set_attr "length" "8")]) -(define_split - [(set (match_operand:HI 0 "bit_register_indirect_operand") - (ior:HI (match_operand:HI 1 "bit_register_indirect_operand") - (match_operand:HI 2 "single_one_operand")))] - "TARGET_H8300SX" - [(set (match_dup 0) - (ior:QI (match_dup 1) - (match_dup 2)))] - { - if (abs (INTVAL (operands[2])) > 0xFF) - { - operands[0] = adjust_address (operands[0], QImode, 0); - operands[1] = adjust_address (operands[1], QImode, 0); - operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); - } - else - { - operands[0] = adjust_address (operands[0], QImode, 1); - operands[1] = adjust_address (operands[1], QImode, 1); - } - }) - -(define_insn "bsethi_msx" +(define_insn "bhi_msx" [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m") - (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") + (ors:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") (match_operand:HI 2 "single_one_operand" "Y2")))] "TARGET_H8300SX" - "bset\\t%V2,%0" + { return == IOR ? "bset\\t%V2,%0" : "bnot\\t%V2,%0"; } [(set_attr "length" "8")]) -(define_insn "iorqi3_1" +(define_insn "qi3_1" [(set (match_operand:QI 0 "bit_operand" "=U,rQ") - (ior:QI (match_operand:QI 1 "bit_operand" "%0,0") + (ors:QI (match_operand:QI 1 "bit_operand" "%0,0") (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))] "TARGET_H8300SX || register_operand (operands[0], QImode) || single_one_operand (operands[2], QImode)" - "@ - bset\\t%V2,%R0 - or\\t%X2,%X0" - [(set_attr "length" "8,*") - (set_attr "length_table" "*,logicb") - (set_attr "cc" "none_0hit,set_znv")]) - -(define_expand "ior3" - [(set (match_operand:QHSI 0 "register_operand" "") - (ior:QHSI (match_operand:QHSI 1 "register_operand" "") - (match_operand:QHSI 2 "h8300_src_operand" "")))] - "" - "") - -;; ---------------------------------------------------------------------- -;; XOR INSTRUCTIONS -;; ---------------------------------------------------------------------- - -(define_insn "bnotqi_msx" - [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU") - (xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0") - (match_operand:QI 2 "single_one_operand" "Y2")))] - "TARGET_H8300SX - && rtx_equal_p (operands[0], operands[1])" - "bnot\\t%V2,%0" - [(set_attr "length" "8")]) - -(define_split - [(set (match_operand:HI 0 "bit_register_indirect_operand") - (xor:HI (match_operand:HI 1 "bit_register_indirect_operand") - (match_operand:HI 2 "single_one_operand")))] - "TARGET_H8300SX" - [(set (match_dup 0) - (xor:QI (match_dup 1) - (match_dup 2)))] { - if (abs (INTVAL (operands[2])) > 0xFF) - { - operands[0] = adjust_address (operands[0], QImode, 0); - operands[1] = adjust_address (operands[1], QImode, 0); - operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); - } - else - { - operands[0] = adjust_address (operands[0], QImode, 1); - operands[1] = adjust_address (operands[1], QImode, 1); - } - }) - -(define_insn "bnothi_msx" - [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m") - (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0") - (match_operand:HI 2 "single_one_operand" "Y2")))] - "TARGET_H8300SX" - "bnot\\t%V2,%0" - [(set_attr "length" "8")]) - -(define_insn "xorqi3_1" - [(set (match_operand:QI 0 "bit_operand" "=U,r") - (xor:QI (match_operand:QI 1 "bit_operand" "%0,0") - (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))] - "TARGET_H8300SX || register_operand (operands[0], QImode) - || single_one_operand (operands[2], QImode)" - "@ - bnot\\t%V2,%R0 - xor\\t%X2,%X0" + if (which_alternative == 0) + return == IOR ? "bset\\t%V2,%R0" : "bnot\\t%V2,%R0"; + else if (which_alternative == 1) + return == IOR ? "or\\t%X2,%X0" : "xor\\t%X2,%X0"; + } [(set_attr "length" "8,*") (set_attr "length_table" "*,logicb") (set_attr "cc" "none_0hit,set_znv")]) -(define_expand "xor3" +(define_expand "3" [(set (match_operand:QHSI 0 "register_operand" "") - (xor:QHSI (match_operand:QHSI 1 "register_operand" "") + (ors:QHSI (match_operand:QHSI 1 "register_operand" "") (match_operand:QHSI 2 "h8300_src_operand" "")))] "" "")