From patchwork Wed Jun 4 00:07:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Jones, Joel" X-Patchwork-Id: 355681 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BA95914007E for ; Wed, 4 Jun 2014 10:07:57 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:content-type:content-id :content-transfer-encoding:mime-version; q=dns; s=default; b=MMq lewuAWLvWbaiP+w97zplw1LhNsWO22LKOFrhb7Swcl5ZmKIdkJsIlpZrzI9bx7HE kPnLEg++6f3uf451o++4vcx95/u65HTH4tLcrpMAZ3K3UIOS12C/QaQy5rq8gzjC IG7kW56qZz4HOrx4Z9+lISfAuFZ8ug+zuJhkjDBQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:content-type:content-id :content-transfer-encoding:mime-version; s=default; bh=3LRHV0zwN ZA1+x6tPwDuWSvr+0w=; b=e911iY3IC4LpiSU3u10Qz2e0j3XKHavBvefRNqU+E IAl9/tgDBu7OAPHI2do/jARGs7SfZeWxRMVcaRl+hmqBh/UqUoaySgHzi12yAFzO GZSewH8c/ObGHvSFPMIQ+x4AnZJgF/Vo0cHwYqfQQM5bAxzAvEapxaifHOKeIebw 1o= Received: (qmail 31739 invoked by alias); 4 Jun 2014 00:07:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 31728 invoked by uid 89); 4 Jun 2014 00:07:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, MIME_BASE64_BLANKS, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS autolearn=ham version=3.3.2 X-HELO: na01-bn1-obe.outbound.protection.outlook.com Received: from mail-bn1blp0188.outbound.protection.outlook.com (HELO na01-bn1-obe.outbound.protection.outlook.com) (207.46.163.188) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 04 Jun 2014 00:07:47 +0000 Received: from DM2PR07MB349.namprd07.prod.outlook.com (10.141.101.154) by DM2PR07MB351.namprd07.prod.outlook.com (10.141.101.148) with Microsoft SMTP Server (TLS) id 15.0.954.9; Wed, 4 Jun 2014 00:07:42 +0000 Received: from DM2PR07MB349.namprd07.prod.outlook.com ([169.254.11.66]) by DM2PR07MB349.namprd07.prod.outlook.com ([169.254.11.66]) with mapi id 15.00.0954.000; Wed, 4 Jun 2014 00:07:42 +0000 From: "Jones, Joel" To: "gcc-patches@gcc.gnu.org" Subject: [AArch64, PATCH] Refactor acquire/release determination into output template Date: Wed, 4 Jun 2014 00:07:42 +0000 Message-ID: <92B71FDE-F4D5-43D6-9BAF-23D5DC02850A@caviumnetworks.com> x-microsoft-antispam: BL:0; ACTION:Default; RISK:Low; SCL:0; SPMLVL:NotSpam; PCL:0; RULEID: x-forefront-prvs: 0232B30BBC x-forefront-antispam-report: SFV:NSPM; SFS:(6009001)(428001)(189002)(199002)(164054003)(74662001)(82746002)(31966008)(101416001)(74502001)(99396002)(4396001)(54356999)(83716003)(83072002)(85852003)(21056001)(87936001)(50986999)(2656002)(86362001)(36756003)(92566001)(92726001)(64706001)(20776003)(66066001)(81342001)(80022001)(19580395003)(79102001)(83322001)(33656002)(99286001)(77982001)(46102001)(76482001)(81542001)(104396001); DIR:OUT; SFP:; SCL:1; SRVR:DM2PR07MB351; H:DM2PR07MB349.namprd07.prod.outlook.com; FPR:; MLV:sfv; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (: caviumnetworks.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Joel.Jones@caviumnetworks.com; Content-ID: <709B5DDA0A39764B8C1341B85316E6FE@caviumnetworks.microsoftonline.com> MIME-Version: 1.0 X-OriginatorOrg: caviumnetworks.com There is duplicate code for determining whether a load or store instruction needs acquire or release semantics. This patch removes the duplicated code and uses a modifying operator to output a/l instead. Since the testsuite already contains tests for the atomic functions, no new testcases are needed. OK? Built and tested for aarch64-elf using Cavium's internal simulator with no regressions. Thanks, Joel Jones ChangeLog: * config/aarch64/aarch64.c (aarch64_print_operand): Add 'Q' and 'R' operator modifiers. * config/aarch64/atomics.md (atomic_load): Use 'Q' instead of returning a different template for acquire. ​ (aarch64_load_exclusive): ​Likewise. (atomic_store): Use 'R' instead of returning a different template for release. (aarch64_store_exclusive): Likewise. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c2f6c4f..56152a0 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3931,6 +3931,50 @@ aarch64_print_operand (FILE *f, rtx x, char code) output_addr_const (asm_out_file, x); break; + case 'Q': + { + /* Print "a" if memory model requires ac'Q'uire semantics */ + if (GET_CODE (x) != CONST_INT) + { + output_operand_lossage ("invalid operand for '%%%c'", code); + return; + } + enum memmodel model = (enum memmodel) INTVAL (x); + bool is_acq = false; + switch (model) + { + default: is_acq = true; break; + case MEMMODEL_RELAXED: + case MEMMODEL_CONSUME: + case MEMMODEL_RELEASE: break; + } + if (is_acq) + fputc ('a', f); + } + break; + + case 'R': + { + /* Print "l" if memory model requires 'R'elease semantics */ + if (GET_CODE (x) != CONST_INT) + { + output_operand_lossage ("invalid operand for '%%%c'", code); + return; + } + enum memmodel model = (enum memmodel) INTVAL (x); + bool is_rel = false; + switch (model) + { + default: is_rel = true; break; + case MEMMODEL_RELAXED: + case MEMMODEL_CONSUME: + case MEMMODEL_ACQUIRE: break; + } + if (is_rel) + fputc ('l', f); + } + break; + default: output_operand_lossage ("invalid operand prefix '%%%c'", code); return; diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index bffa465..55ba918 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -259,15 +259,7 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPECV_LDA))] "" - { - enum memmodel model = (enum memmodel) INTVAL (operands[2]); - if (model == MEMMODEL_RELAXED - || model == MEMMODEL_CONSUME - || model == MEMMODEL_RELEASE) - return "ldr\t%0, %1"; - else - return "ldar\t%0, %1"; - } + "ld%Q2r\t%0, %1" ) (define_insn "atomic_store" @@ -277,15 +269,7 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPECV_STL))] "" - { - enum memmodel model = (enum memmodel) INTVAL (operands[2]); - if (model == MEMMODEL_RELAXED - || model == MEMMODEL_CONSUME - || model == MEMMODEL_ACQUIRE) - return "str\t%1, %0"; - else - return "stlr\t%1, %0"; - } + "st%R2r\t%1, %0" ) (define_insn "aarch64_load_exclusive" @@ -296,15 +280,7 @@ (match_operand:SI 2 "const_int_operand")] UNSPECV_LX)))] "" - { - enum memmodel model = (enum memmodel) INTVAL (operands[2]); - if (model == MEMMODEL_RELAXED - || model == MEMMODEL_CONSUME - || model == MEMMODEL_RELEASE) - return "ldxr\t%w0, %1"; - else - return "ldaxr\t%w0, %1"; - } + "ld%Q2xr\t%w0, %1" ) (define_insn "aarch64_load_exclusive" @@ -314,15 +290,7 @@ (match_operand:SI 2 "const_int_operand")] UNSPECV_LX))] "" - { - enum memmodel model = (enum memmodel) INTVAL (operands[2]); - if (model == MEMMODEL_RELAXED - || model == MEMMODEL_CONSUME - || model == MEMMODEL_RELEASE) - return "ldxr\t%0, %1"; - else - return "ldaxr\t%0, %1"; - } + "ld%Q2xr\t%0, %1" ) (define_insn "aarch64_store_exclusive" @@ -334,15 +302,7 @@ (match_operand:SI 3 "const_int_operand")] UNSPECV_SX))] "" - { - enum memmodel model = (enum memmodel) INTVAL (operands[3]); - if (model == MEMMODEL_RELAXED - || model == MEMMODEL_CONSUME - || model == MEMMODEL_ACQUIRE) - return "stxr\t%w0, %2, %1"; - else - return "stlxr\t%w0, %2, %1"; - } + "st%R3xr\t%w0, %2, %1"; ) (define_expand "mem_thread_fence"