@@ -2898,26 +2898,29 @@ (define_expand "and<mode>3"
DONE;
}
- if (rs6000_is_valid_and_mask (operands[2], <MODE>mode))
+ if (CONST_INT_P (operands[2]))
{
- emit_insn (gen_and<mode>3_mask (operands[0], operands[1], operands[2]));
- DONE;
- }
+ if (rs6000_is_valid_and_mask (operands[2], <MODE>mode))
+ {
+ emit_insn (gen_and<mode>3_mask (operands[0], operands[1], operands[2]));
+ DONE;
+ }
- if (logical_const_operand (operands[2], <MODE>mode)
- && rs6000_gen_cell_microcode)
- {
- emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
- DONE;
- }
+ if (logical_const_operand (operands[2], <MODE>mode)
+ && rs6000_gen_cell_microcode)
+ {
+ emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
+ DONE;
+ }
- if (rs6000_is_valid_2insn_and (operands[2], <MODE>mode))
- {
- rs6000_emit_2insn_and (<MODE>mode, operands, true, 0);
- DONE;
- }
+ if (rs6000_is_valid_2insn_and (operands[2], <MODE>mode))
+ {
+ rs6000_emit_2insn_and (<MODE>mode, operands, true, 0);
+ DONE;
+ }
- operands[2] = force_reg (<MODE>mode, operands[2]);
+ operands[2] = force_reg (<MODE>mode, operands[2]);
+ }
})