| Message ID | 894B9D8AA7173E40BFFBBF195B8281BCB76A18@SZXEMI503-MBX.china.huawei.com |
|---|---|
| State | New |
| Headers | show |
On Wed, 10 Jun 2015, weixiangyu wrote: > + if (bitsize + bitnum > unit && bitnum < unit) > + { > + warning (OPT_Wextra, "write of "HOST_WIDE_INT_PRINT_UNSIGNED"bit data " > + "outside the bound of destination object, data truncated into " > + HOST_WIDE_INT_PRINT_UNSIGNED"bit", bitsize, unit - bitnum); HOST_WIDE_INT_PRINT_UNSIGNED is a printf format, which depends on the host and is not suitable for any translatable string, not a format for GCC's pretty printers. Use %wu instead in any call to a GCC diagnostic function. Mainline appears to have this correct.
On 10 June 2015 at 03:46, weixiangyu <weixiangyu@huawei.com> wrote: > Updated patches were attached. Rebased on the latest 4.9 branch. > Tested on aarch64-linux (big-endian and little-endian) with qemu. > OK for 4.9? Hi, > And the second one: The original r215046 mainline commit contains a test case that is omitted from the proposed back port, can you elaborate why you have chosen to drop the test case? The usual convention on this list is to post one patch per email such that each email thread discusses just one patch. Thanks /Marcus > Index: gcc/ChangeLog > =================================================================== > --- gcc/ChangeLog (revision 223867) > +++ gcc/ChangeLog (working copy) > @@ -1,3 +1,28 @@ > +2015-06-09 Xiangyu Wei <weixiangyu@huawei.com> > + > + Backport from mainline r215046: > + 2014-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com> > + PR target/61749 > + * config/aarch64/aarch64-builtins.c (aarch64_types_quadop_qualifiers): > + Use qualifier_immediate for last operand. Rename to... > + (aarch64_types_ternop_lane_qualifiers): ... This. > + (TYPES_QUADOP): Rename to... > + (TYPES_TERNOP_LANE): ... This. > + (aarch64_simd_expand_args): Return const0_rtx when encountering user > + error. Change return of 0 to return of NULL_RTX. > + (aarch64_crc32_expand_builtin): Likewise. > + (aarch64_expand_builtin): Return NULL_RTX instead of 0. > + ICE when expanding unknown builtin. > + * config/aarch64/aarch64-simd-builtins.def (sqdmlal_lane): Use > + TERNOP_LANE qualifiers. > + (sqdmlsl_lane): Likewise. > + (sqdmlal_laneq): Likewise. > + (sqdmlsl_laneq): Likewise. > + (sqdmlal2_lane): Likewise. > + (sqdmlsl2_lane): Likewise. > + (sqdmlal2_laneq): Likewise. > + (sqdmlsl2_laneq): Likewise. > + * gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c: New test. > Index: gcc/config/aarch64/aarch64-builtins.c > =================================================================== > --- gcc/config/aarch64/aarch64-builtins.c (revision 223867) > +++ gcc/config/aarch64/aarch64-builtins.c (working copy) > @@ -172,10 +172,10 @@ aarch64_types_ternopu_qualifiers[SIMD_MAX_BUILTIN_ > #define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers) > > static enum aarch64_type_qualifiers > -aarch64_types_quadop_qualifiers[SIMD_MAX_BUILTIN_ARGS] > +aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_none, qualifier_none, > - qualifier_none, qualifier_none }; > -#define TYPES_QUADOP (aarch64_types_quadop_qualifiers) > + qualifier_none, qualifier_immediate }; > +#define TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers) > > static enum aarch64_type_qualifiers > aarch64_types_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS] > @@ -818,8 +818,11 @@ aarch64_simd_expand_args (rtx target, int icode, i > case SIMD_ARG_CONSTANT: > if (!(*insn_data[icode].operand[argc + have_retval].predicate) > (op[argc], mode[argc])) > - error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, " > + { > + error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, " > "expected %<const int%>", argc + 1); > + return const0_rtx; > + } > break; > > case SIMD_ARG_STOP: > @@ -886,7 +889,7 @@ aarch64_simd_expand_args (rtx target, int icode, i > } > > if (!pat) > - return 0; > + return NULL_RTX; > >> -----Original Message----- >> From: James Greenhalgh [mailto:james.greenhalgh@arm.com] >> Sent: Thursday, May 28, 2015 9:58 PM >> To: weixiangyu >> Cc: gcc-patches@gcc.gnu.org; Marcus Shawcroft; Richard Earnshaw; Yangfei >> (Felix) >> Subject: Re: backport the fixes of PR target/64011 and /61749 to 4.9 gcc >> >> On Wed, May 27, 2015 at 03:49:24AM +0100, weixiangyu wrote: >> > Hi, >> >> Hi, >> >> > The first patch backports the fix of PR >> > target/64011(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64011) to >> > the 4.9 branch from trunk r219717, >> >> I can't approve this patch to be backported, so please do not commit it without >> approval from the appropriate maintainer. >> >> > and the second patch backports the fix of PR >> > target/61749(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61749) to >> > the 4.9 branch from trunk r215046. >> >> This second patch is OK to backport to 4.9. It is a harmelss enough patch which >> fixes an ICE. >> >> Thanks, >> James >> >> > And the second one: >> > >> ================================================================ >> === >> > --- gcc/ChangeLog-HCC (revision 130589) >> > +++ gcc/ChangeLog-HCC (revision 130590) >> > @@ -1,3 +1,29 @@ >> > +2015-05-26 y00166676 <felix.yang@huawei.com> >> > + >> > + Backport from trunk r215046. >> > + 2014-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com> >> > + >> > + PR target/61749 >> > + * config/aarch64/aarch64-builtins.c >> (aarch64_types_quadop_qualifiers): >> > + Use qualifier_immediate for last operand. Rename to... >> > + (aarch64_types_ternop_lane_qualifiers): ... This. >> > + (TYPES_QUADOP): Rename to... >> > + (TYPES_TERNOP_LANE): ... This. >> > + (aarch64_simd_expand_args): Return const0_rtx when >> encountering user >> > + error. Change return of 0 to return of NULL_RTX. >> > + (aarch64_crc32_expand_builtin): Likewise. >> > + (aarch64_expand_builtin): Return NULL_RTX instead of 0. >> > + ICE when expanding unknown builtin. >> > + * config/aarch64/aarch64-simd-builtins.def (sqdmlal_lane): Use >> > + TERNOP_LANE qualifiers. >> > + (sqdmlsl_lane): Likewise. >> > + (sqdmlal_laneq): Likewise. >> > + (sqdmlsl_laneq): Likewise. >> > + (sqdmlal2_lane): Likewise. >> > + (sqdmlsl2_lane): Likewise. >> > + (sqdmlal2_laneq): Likewise. >> > + (sqdmlsl2_laneq): Likewise. >> > + >> > * gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c: New test. >> > >> >
I didn't drop the test case and i have tested that case on my manchine(aarch64-linux) with qemu. I am sorry I forgot to add the testcase in the last patch. A new patch was added to the accessory. I am a new guy to the community and I will try my best to accord with the norm of the community next time. Sorry for my careless. Many thanks /Xiangyu Wei > -----Original Message----- > From: Marcus Shawcroft [mailto:marcus.shawcroft@gmail.com] > Sent: Thursday, June 11, 2015 5:25 PM > To: weixiangyu > Cc: James Greenhalgh; gcc-patches@gcc.gnu.org; Marcus Shawcroft; Richard > Earnshaw > Subject: Re: backport the fixes of PR target/64011 and /61749 to 4.9 gcc > > On 10 June 2015 at 03:46, weixiangyu <weixiangyu@huawei.com> wrote: > > Updated patches were attached. Rebased on the latest 4.9 branch. > > Tested on aarch64-linux (big-endian and little-endian) with qemu. > > OK for 4.9? > > > Hi, > > > And the second one: > > The original r215046 mainline commit contains a test case that is omitted from > the proposed back port, can you elaborate why you have chosen to drop the > test case? > > The usual convention on this list is to post one patch per email such that each > email thread discusses just one patch. > > Thanks > /Marcus > > > > Index: gcc/ChangeLog > > > ================================================================ > === > > --- gcc/ChangeLog (revision 223867) > > +++ gcc/ChangeLog (working copy) > > @@ -1,3 +1,28 @@ > > +2015-06-09 Xiangyu Wei <weixiangyu@huawei.com> > > + > > + Backport from mainline r215046: > > + 2014-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com> > > + PR target/61749 > > + * config/aarch64/aarch64-builtins.c > (aarch64_types_quadop_qualifiers): > > + Use qualifier_immediate for last operand. Rename to... > > + (aarch64_types_ternop_lane_qualifiers): ... This. > > + (TYPES_QUADOP): Rename to... > > + (TYPES_TERNOP_LANE): ... This. > > + (aarch64_simd_expand_args): Return const0_rtx when > encountering user > > + error. Change return of 0 to return of NULL_RTX. > > + (aarch64_crc32_expand_builtin): Likewise. > > + (aarch64_expand_builtin): Return NULL_RTX instead of 0. > > + ICE when expanding unknown builtin. > > + * config/aarch64/aarch64-simd-builtins.def (sqdmlal_lane): Use > > + TERNOP_LANE qualifiers. > > + (sqdmlsl_lane): Likewise. > > + (sqdmlal_laneq): Likewise. > > + (sqdmlsl_laneq): Likewise. > > + (sqdmlal2_lane): Likewise. > > + (sqdmlsl2_lane): Likewise. > > + (sqdmlal2_laneq): Likewise. > > + (sqdmlsl2_laneq): Likewise. > > + * gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c: New test. > > Index: gcc/config/aarch64/aarch64-builtins.c > > > ================================================================ > === > > --- gcc/config/aarch64/aarch64-builtins.c (revision 223867) > > +++ gcc/config/aarch64/aarch64-builtins.c (working copy) > > @@ -172,10 +172,10 @@ > > aarch64_types_ternopu_qualifiers[SIMD_MAX_BUILTIN_ > > #define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers) > > > > static enum aarch64_type_qualifiers > > -aarch64_types_quadop_qualifiers[SIMD_MAX_BUILTIN_ARGS] > > +aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] > > = { qualifier_none, qualifier_none, qualifier_none, > > - qualifier_none, qualifier_none }; > > -#define TYPES_QUADOP (aarch64_types_quadop_qualifiers) > > + qualifier_none, qualifier_immediate }; #define > > +TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers) > > > > static enum aarch64_type_qualifiers > > aarch64_types_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS] > > @@ -818,8 +818,11 @@ aarch64_simd_expand_args (rtx target, int icode, i > > case SIMD_ARG_CONSTANT: > > if (!(*insn_data[icode].operand[argc + > have_retval].predicate) > > (op[argc], mode[argc])) > > - error_at (EXPR_LOCATION (exp), "incompatible type for > argument %d, " > > + { > > + error_at (EXPR_LOCATION (exp), "incompatible type > for argument %d, " > > "expected %<const int%>", argc + 1); > > + return const0_rtx; > > + } > > break; > > > > case SIMD_ARG_STOP: > > @@ -886,7 +889,7 @@ aarch64_simd_expand_args (rtx target, int icode, i > > } > > > > if (!pat) > > - return 0; > > + return NULL_RTX; > > > >> -----Original Message----- > >> From: James Greenhalgh [mailto:james.greenhalgh@arm.com] > >> Sent: Thursday, May 28, 2015 9:58 PM > >> To: weixiangyu > >> Cc: gcc-patches@gcc.gnu.org; Marcus Shawcroft; Richard Earnshaw; > >> Yangfei > >> (Felix) > >> Subject: Re: backport the fixes of PR target/64011 and /61749 to 4.9 > >> gcc > >> > >> On Wed, May 27, 2015 at 03:49:24AM +0100, weixiangyu wrote: > >> > Hi, > >> > >> Hi, > >> > >> > The first patch backports the fix of PR > >> > target/64011(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64011) to > >> > the 4.9 branch from trunk r219717, > >> > >> I can't approve this patch to be backported, so please do not commit > >> it without approval from the appropriate maintainer. > >> > >> > and the second patch backports the fix of PR > >> > target/61749(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61749) to > >> > the 4.9 branch from trunk r215046. > >> > >> This second patch is OK to backport to 4.9. It is a harmelss enough > >> patch which fixes an ICE. > >> > >> Thanks, > >> James > >> > >> > And the second one: > >> > > >> > ================================================================ > >> === > >> > --- gcc/ChangeLog-HCC (revision 130589) > >> > +++ gcc/ChangeLog-HCC (revision 130590) > >> > @@ -1,3 +1,29 @@ > >> > +2015-05-26 y00166676 <felix.yang@huawei.com> > >> > + > >> > + Backport from trunk r215046. > >> > + 2014-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com> > >> > + > >> > + PR target/61749 > >> > + * config/aarch64/aarch64-builtins.c > >> (aarch64_types_quadop_qualifiers): > >> > + Use qualifier_immediate for last operand. Rename to... > >> > + (aarch64_types_ternop_lane_qualifiers): ... This. > >> > + (TYPES_QUADOP): Rename to... > >> > + (TYPES_TERNOP_LANE): ... This. > >> > + (aarch64_simd_expand_args): Return const0_rtx when > >> encountering user > >> > + error. Change return of 0 to return of NULL_RTX. > >> > + (aarch64_crc32_expand_builtin): Likewise. > >> > + (aarch64_expand_builtin): Return NULL_RTX instead of 0. > >> > + ICE when expanding unknown builtin. > >> > + * config/aarch64/aarch64-simd-builtins.def (sqdmlal_lane): Use > >> > + TERNOP_LANE qualifiers. > >> > + (sqdmlsl_lane): Likewise. > >> > + (sqdmlal_laneq): Likewise. > >> > + (sqdmlsl_laneq): Likewise. > >> > + (sqdmlal2_lane): Likewise. > >> > + (sqdmlsl2_lane): Likewise. > >> > + (sqdmlal2_laneq): Likewise. > >> > + (sqdmlsl2_laneq): Likewise. > >> > + > >> > * gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c: New test. > >> > > >> > >
Index: gcc/ChangeLog =================================================================== --- gcc/ChangeLog (revision 223867) +++ gcc/ChangeLog (working copy) @@ -1,3 +1,11 @@ +2015-06-09 Xiangyu Wei <weixiangyu@huawei.com> + + Backport from mainline r219717: + 2015-01-15 Jiong Wang <jiong.wang@arm.com> + PR rtl-optimization/64011 + * expmed.c (store_bit_field_using_insv): Warn and truncate bitsize when + there is partial overflow. + Index: gcc/expmed.c =================================================================== --- gcc/expmed.c (revision 223867) +++ gcc/expmed.c (working copy) @@ -539,7 +539,21 @@ store_bit_field_using_insv (const extraction_insn xop0 = tem; copy_back = true; } - + + /* There are similar overflow check at the start of store_bit_field_1, + but that only check the situation where the field lies completely + outside the register, while there do have situation where the field + lies partialy in the register, we need to adjust bitsize for this + partial overflow situation. Without this fix, pr48335-2.c on big-endian + will broken on those arch support bit insert instruction, like arm, aarch64 + etc. */ + if (bitsize + bitnum > unit && bitnum < unit) + { + warning (OPT_Wextra, "write of "HOST_WIDE_INT_PRINT_UNSIGNED"bit data " + "outside the bound of destination object, data truncated into " + HOST_WIDE_INT_PRINT_UNSIGNED"bit", bitsize, unit - bitnum); + bitsize = unit - bitnum; + } /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count "backwards" from the size of the unit we are inserting into. Otherwise, we count bits from the most significant on a And the second one: Index: gcc/ChangeLog =================================================================== --- gcc/ChangeLog (revision 223867) +++ gcc/ChangeLog (working copy) @@ -1,3 +1,28 @@ +2015-06-09 Xiangyu Wei <weixiangyu@huawei.com> + + Backport from mainline r215046: + 2014-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + PR target/61749 + * config/aarch64/aarch64-builtins.c (aarch64_types_quadop_qualifiers): + Use qualifier_immediate for last operand. Rename to... + (aarch64_types_ternop_lane_qualifiers): ... This. + (TYPES_QUADOP): Rename to... + (TYPES_TERNOP_LANE): ... This. + (aarch64_simd_expand_args): Return const0_rtx when encountering user + error. Change return of 0 to return of NULL_RTX. + (aarch64_crc32_expand_builtin): Likewise. + (aarch64_expand_builtin): Return NULL_RTX instead of 0. + ICE when expanding unknown builtin. + * config/aarch64/aarch64-simd-builtins.def (sqdmlal_lane): Use + TERNOP_LANE qualifiers. + (sqdmlsl_lane): Likewise. + (sqdmlal_laneq): Likewise. + (sqdmlsl_laneq): Likewise. + (sqdmlal2_lane): Likewise. + (sqdmlsl2_lane): Likewise. + (sqdmlal2_laneq): Likewise. + (sqdmlsl2_laneq): Likewise. + * gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c: New test. Index: gcc/config/aarch64/aarch64-builtins.c =================================================================== --- gcc/config/aarch64/aarch64-builtins.c (revision 223867) +++ gcc/config/aarch64/aarch64-builtins.c (working copy) @@ -172,10 +172,10 @@ aarch64_types_ternopu_qualifiers[SIMD_MAX_BUILTIN_ #define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers) static enum aarch64_type_qualifiers -aarch64_types_quadop_qualifiers[SIMD_MAX_BUILTIN_ARGS] +aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_none, - qualifier_none, qualifier_none }; -#define TYPES_QUADOP (aarch64_types_quadop_qualifiers) + qualifier_none, qualifier_immediate }; +#define TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers) static enum aarch64_type_qualifiers aarch64_types_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS] @@ -818,8 +818,11 @@ aarch64_simd_expand_args (rtx target, int icode, i case SIMD_ARG_CONSTANT: if (!(*insn_data[icode].operand[argc + have_retval].predicate) (op[argc], mode[argc])) - error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, " + { + error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, " "expected %<const int%>", argc + 1); + return const0_rtx; + } break; case SIMD_ARG_STOP: @@ -886,7 +889,7 @@ aarch64_simd_expand_args (rtx target, int icode, i } if (!pat) - return 0; + return NULL_RTX; > -----Original Message----- > From: James Greenhalgh [mailto:james.greenhalgh@arm.com]