Message ID | 87zk3uksj2.fsf@talisman.home |
---|---|
State | New |
Headers | show |
On Wed, 10 Oct 2012, Richard Sandiford wrote: > > I've thought of -miterative-mdu or suchlike a knob that would override > > the default cost of multiplication/division as appropriate (i.e. to 32/64 > > plus any extra operation-specific constant as required), perhaps by > > forcing the 4Kp insn reservation (extended to 64 bits as required) over > > the usual one; of course there would be nothing to override the -mtune=4Kp > > arrangement with. Nothing urgent though, just an idea to ponder. > > FWIW, using the 4Kp reservation itself wouldn't necessarily work, > because all modern scheduling descriptions define their own CPU units. > You'd probably need to add new reservations to each affected MIPS32 > and MIPS64 .md file. Thanks for the hint. I have skimmed through documentation I have available and the following MTI processors implement an iterative MDU as an RTL option: M4K, M14K, M14Kc, and the following ones always have one: 4Kp, 4KEp. No 64-bit MTI processor had it so far it would seem (the 5K chips have an iterative divider and a high-performance multiplier). We currently have no pipeline descriptions for any of the M cores, so my concern seemed to be a little bit premature (though still valid of course). The option proposed will only be needed once/if we get any of the respective pipeline descriptions. Arguably anyone targetting them is likely going to be after -Os anyway, although at least with the M14Kc I think it should not be taken for granted. We're missing a pipeline description for the 4KE-family cores as well. If not adding costs for the extra MIPS32r2 additions I think at the very least we should trivially enable the existing bits of 4k.md for these cores; the pipeline is the same across the whole 4K/4KE family and it's only the extra instructions that have been added with the E update. Maciej
Index: gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c =================================================================== --- gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c 2012-10-07 09:45:04.000000000 +0100 +++ gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c 2012-10-10 20:51:44.402528138 +0100 @@ -5,7 +5,8 @@ /* { dg-skip-if "requires register frequencies" { *-*-* } { "-O0" "-Os" } { "" } } */ /* Check that the zero-initialization of the accumulator feeding into - the madd is done by means of a mult instruction instead of mthi/mtlo. */ + the madd is done by means of an mthi & mtlo pair instead of a + "mult $0,$0" instruction. */ NOMIPS16 long long f (int n, int *v, int m) {