Index: gcc/config/aarch64/iterators.md
===================================================================
--- gcc/config/aarch64/iterators.md	2018-07-31 19:10:15.744291661 +0100
+++ gcc/config/aarch64/iterators.md	2018-08-03 16:32:07.531492221 +0100
@@ -1537,8 +1537,6 @@ (define_int_iterator FCVT [UNSPEC_FRINTZ
 (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
 (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
 
-(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
-
 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
                           UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
                           UNSPEC_CRC32CW UNSPEC_CRC32CX])
@@ -1788,8 +1786,6 @@ (define_int_attr hi_lanes_optab [(UNSPEC
 				 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
 				 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
 
-(define_int_attr frecp_suffix  [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
-
 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
                         (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
                         (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
Index: gcc/config/aarch64/aarch64-simd.md
===================================================================
--- gcc/config/aarch64/aarch64-simd.md	2018-08-02 11:59:06.851355923 +0100
+++ gcc/config/aarch64/aarch64-simd.md	2018-08-03 16:32:07.531492221 +0100
@@ -5879,21 +5879,22 @@ (define_insn "aarch64_simd_ld1<mode>_x2"
 
 
 (define_insn "@aarch64_frecpe<mode>"
-  [(set (match_operand:VHSDF 0 "register_operand" "=w")
-	(unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")]
+  [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w")
+	(unspec:VHSDF_HSDF
+	 [(match_operand:VHSDF_HSDF 1 "register_operand" "w")]
 	 UNSPEC_FRECPE))]
   "TARGET_SIMD"
-  "frecpe\\t%0.<Vtype>, %1.<Vtype>"
+  "frecpe\t%<v>0<Vmtype>, %<v>1<Vmtype>"
   [(set_attr "type" "neon_fp_recpe_<stype><q>")]
 )
 
-(define_insn "aarch64_frecp<FRECP:frecp_suffix><mode>"
+(define_insn "aarch64_frecpx<mode>"
   [(set (match_operand:GPF_F16 0 "register_operand" "=w")
 	(unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")]
-	 FRECP))]
+	 UNSPEC_FRECPX))]
   "TARGET_SIMD"
-  "frecp<FRECP:frecp_suffix>\\t%<s>0, %<s>1"
-  [(set_attr "type" "neon_fp_recp<FRECP:frecp_suffix>_<GPF_F16:stype>")]
+  "frecpx\t%<s>0, %<s>1"
+  [(set_attr "type" "neon_fp_recpx_<GPF_F16:stype>")]
 )
 
 (define_insn "@aarch64_frecps<mode>"
Index: gcc/config/aarch64/aarch64-simd-builtins.def
===================================================================
--- gcc/config/aarch64/aarch64-simd-builtins.def	2018-06-14 12:27:40.672026808 +0100
+++ gcc/config/aarch64/aarch64-simd-builtins.def	2018-08-03 16:32:07.531492221 +0100
@@ -413,8 +413,6 @@
   BUILTIN_VALL (BINOP, trn1, 0)
   BUILTIN_VALL (BINOP, trn2, 0)
 
-  /* Implemented by
-     aarch64_frecp<FRECP:frecp_suffix><mode>.  */
   BUILTIN_GPF_F16 (UNOP, frecpe, 0)
   BUILTIN_GPF_F16 (UNOP, frecpx, 0)
 
Index: gcc/testsuite/gcc.target/aarch64/frecpe_1.c
===================================================================
--- /dev/null	2018-07-26 10:26:13.137955424 +0100
+++ gcc/testsuite/gcc.target/aarch64/frecpe_1.c	2018-08-03 16:32:07.531492221 +0100
@@ -0,0 +1,18 @@
+/* { dg-options "-Ofast -mlow-precision-div" } */
+/* { dg-do compile } */
+
+float
+f1 (float x)
+{
+  return 1 / x;
+}
+
+/* { dg-final { scan-assembler {\tfrecpe\t(s[0-9]+), s0\n\tfrecps\t(s[0-9]+), \1, s0\n\tfmul\ts0, \1, \2\n} } } */
+
+double
+f2 (double x)
+{
+  return 1 / x;
+}
+
+/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t\1, \1, \2\n\tfrecps\t\2, \1, d0\n\tfmul\td0, \1, \2\n} } } */
Index: gcc/testsuite/gcc.target/aarch64/frecpe_2.c
===================================================================
--- /dev/null	2018-07-26 10:26:13.137955424 +0100
+++ gcc/testsuite/gcc.target/aarch64/frecpe_2.c	2018-08-03 16:32:07.531492221 +0100
@@ -0,0 +1,18 @@
+/* { dg-options "-Ofast -mlow-precision-div" } */
+/* { dg-do compile } */
+
+float
+f1 (float x, float y)
+{
+  return y / x;
+}
+
+/* { dg-final { scan-assembler {\tfrecpe\t(s[0-9]+), s0\n\tfrecps\t(s[0-9]+), \1, s0\n\tfmul\t\1, \1, s1\n\tfmul\ts0, \1, \2\n} } } */
+
+double
+f2 (double x, double y)
+{
+  return y / x;
+}
+
+/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t\1, \1, \2\n\tfrecps\t\2, \1, d0\n\tfmul\t\1, \1, d1\n\tfmul\td0, \1, \2\n} } } */
