===================================================================
@@ -1256,6 +1256,41 @@
}
}
+struct decl_chain
+{
+ tree fndecl;
+ struct decl_chain * next;
+};
+
+/* Stack of decls for which we have issued warnings. */
+static struct decl_chain * warned_decls = NULL;
+
+static void
+add_warned_decl (tree fndecl)
+{
+ struct decl_chain * warned = (struct decl_chain *) xmalloc (sizeof * warned);
+
+ warned->fndecl = fndecl;
+ warned->next = warned_decls;
+ warned_decls = warned;
+}
+
+/* Returns TRUE if FNDECL is on our list of warned about decls. */
+
+static bool
+already_warned (tree fndecl)
+{
+ struct decl_chain * warned;
+
+ for (warned = warned_decls;
+ warned != NULL;
+ warned = warned->next)
+ if (warned->fndecl == fndecl)
+ return true;
+
+ return false;
+}
+
/* Perform any actions necessary before starting to compile FNDECL.
For the RX we use this to make sure that we have the correct
set of register masks selected. If FNDECL is NULL then we are
@@ -1288,6 +1323,24 @@
target_reinit ();
}
+ if (current_is_fast_interrupt && rx_warn_multiple_fast_interrupts)
+ {
+ /* We do not warn about the first fast interrupt routine that
+ we see. Instead we just push it onto the stack. */
+ if (warned_decls == NULL)
+ add_warned_decl (fndecl);
+
+ /* Otherwise if this fast interrupt is one for which we have
+ not already issued a warning, generate one and then push
+ it onto the stack as well. */
+ else if (! already_warned (fndecl))
+ {
+ warning (0, "multiple fast interrupt routines seen: %qE and %qE",
+ fndecl, warned_decls->fndecl);
+ add_warned_decl (fndecl);
+ }
+ }
+
rx_previous_fndecl = fndecl;
}
===================================================================
@@ -118,3 +118,9 @@
mpid
Target Mask(PID)
Enables Position-Independent-Data (PID) mode.
+
+;---------------------------------------------------
+
+mwarn-multiple-fast-interrupts
+Target Report Var(rx_warn_multiple_fast_interrupts) Init(1) Warning
+Warn when multiple, different, fast interrupt handlers are in the compilation unit.
===================================================================
@@ -859,6 +859,7 @@
-mmax-constant-size=@gol
-mint-register=@gol
-mpid@gol
+-mno-warn-multiple-fast-interrupts@gol
-msave-acc-in-interrupts}
@emph{S/390 and zSeries Options}
@@ -17875,6 +17876,15 @@
By default this feature is not enabled. The default can be restored
via the @option{-mno-pid} command-line option.
+@item -mno-warn-multiple-fast-interrupts
+@itemx -mwarn-multiple-fast-interrupts
+@opindex mno-warn-multiple-fast-interrupts
+@opindex mwarn-multiple-fast-interrupts
+Prevents GCC from issuing a warning message if it finds more than one
+fast interrupt handler when it is compiling a file. The default is to
+issue a warning for each extra fast interrupt handler found, as the RX
+only supports one such interrupt.
+
@end table
@emph{Note:} The generic GCC command-line option @option{-ffixed-@var{reg}}
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.8/changes.html,v
retrieving revision 1.32
@@ -239,6 +239,14 @@ by this change.</p>
operating systems manage the VRSAVE register directly.</li>
</ul>
+<h3 id="rx">RX</h3>
+ <ul>
+ <li>This target will now issue a warning message whenever multiple fast
+ interrupt handlers are found in the same cpmpilation unit. This feature can
+ be turned off by the new <code>-mno-warn-multiple-fast-interrupts</code>
+ command line option.
+ </ul>
+
<h3 id="sh">SH</h3>
<ul>
<li>The default alignment settings have been reduced to be less aggressive.