From patchwork Wed Nov 25 12:23:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 548512 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 15A8E1401DE for ; Wed, 25 Nov 2015 23:23:42 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=TsCt0sIy; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type:content-transfer-encoding; q=dns; s= default; b=I+4zUWUTfyxs+IEhZA5DXhWfE2RvSyr2dFLc2omCDm7Fm9/H66LT1 mYZdrdI0zlv0OyKOq1xmE/76/14Y7XwWTmICo2LQpIlwUCA+4s0rCmF6E3VNrA6X sMIlzMe2f0mIFJoUvObs3x5Ah3hDJFVhKrDxDce6MQ60ztyobpwfnc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type:content-transfer-encoding; s=default; bh=+xw5aW0QKfpIMfZVVJ2sEZ+VMRU=; b=TsCt0sIyA1Eaw3divs0y6W7jYoJf gRIEHOlTUMdvIaKtY09/9dj0r4BfWWqjSjhkF3w/lGw1B/JrZvbLVXU3yVZK4yd6 YrSF6lFPN4zGV3xvcqKyirUe5fWHGHVxUK8/Bz47clOelFQ19Wbi9C0DhNcFnToI R70X9lYfz9KLhIk= Received: (qmail 108461 invoked by alias); 25 Nov 2015 12:23:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 108427 invoked by uid 89); 25 Nov 2015 12:23:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 25 Nov 2015 12:23:29 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-22-hZx3Kik3SQqNPp9ijLaIXQ-1; Wed, 25 Nov 2015 12:23:23 +0000 Received: from localhost ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 25 Nov 2015 12:23:23 +0000 From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, nickc@redhat.com, richard.earnshaw@arm.com, ramana.radhakrishnan@arm.com, kyrylo.tkachov@arm.com, richard.sandiford@arm.com Cc: nickc@redhat.com, richard.earnshaw@arm.com, ramana.radhakrishnan@arm.com, kyrylo.tkachov@arm.com Subject: [PR68432 02/22][ARM] Remove operand dependency from use_literal_pool References: <874mgajmo9.fsf@e105548-lin.cambridge.arm.com> Date: Wed, 25 Nov 2015 12:23:23 +0000 In-Reply-To: <874mgajmo9.fsf@e105548-lin.cambridge.arm.com> (Richard Sandiford's message of "Wed, 25 Nov 2015 12:20:06 +0000") Message-ID: <87si3ui7yc.fsf@e105548-lin.cambridge.arm.com> User-Agent: Gnus/5.130012 (Ma Gnus v0.12) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 X-MC-Unique: hZx3Kik3SQqNPp9ijLaIXQ-1 This patch is like the previous one in the series, but removes the dependence of use_literal_pool on match_operand. I think this fixes a genuine bug. If we cache the enabled attribute on an insn that happens to have a nonimmediate operand, we'll treat it as enabled for all subsequent insns, regardless of arm_disable_literal_pool. Similarly if we cache the enabled attribute on an insn that happens to have an immediate operand, we'll always treat that alternative as disabled for arm_disable_literal_pool, even if we later see a memory operand. Splitting the alternatives means that we'll always treat the memory alternative as enabled. We'll treat the immediate alternative as enabled iff arm_disable_literal_pool is false. The immediate alternative still has to accept memories because that's how arm_reorg tells whether it can use a constant pool. Tested as described in the covering note. gcc/ * config/arm/arm.md (use_literal_pool): Remove operands test. * config/arm/iwmmxt.md (*iwmmxt_arm_movdi): Split immediate and memory f_load* alternatives. (*iwmmxt_movsi_insn): Likewise. * config/arm/vfp.md (*arm_movsi_vfp): Likewise. (*thumb2_movsi_vfp): Likewise. (*movdi_vfp): Likewise. (*movdi_vfp_cortexa8): Likewise. (*movsf_vfp): Likewise. (*thumb2_movsf_vfp): Likewise. (*movdf_vfp): Likewise. (*thumb2_movdf_vfp): Likewise. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 40666b4..8812d07 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -197,11 +197,7 @@ (const_string "yes")] (const_string "no"))) -(define_attr "use_literal_pool" "no,yes" - (cond [(and (eq_attr "type" "f_loads,f_loadd") - (match_test "CONSTANT_P (operands[1])")) - (const_string "yes")] - (const_string "no"))) +(define_attr "use_literal_pool" "no,yes" (const_string "no")) ; Enable all alternatives that are both arch_enabled and insn_enabled. ; FIXME:: opt_enabled has been temporarily removed till the time we have diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md index d1a60ff..ae30868 100644 --- a/gcc/config/arm/iwmmxt.md +++ b/gcc/config/arm/iwmmxt.md @@ -107,8 +107,8 @@ ) (define_insn "*iwmmxt_arm_movdi" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,r, y,Uy,*w, r,*w,*w, *Uv") - (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r,y,r,y,Uy,y, r,*w,*w,*Uvi,*w"))] + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,r, y,Uy,*w, r,*w,*w, *w, *Uv") + (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r,y,r,y,Uy,y, r,*w,*w,*Uv,*Uvi,*w"))] "TARGET_REALLY_IWMMXT && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" @@ -140,7 +140,7 @@ return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; else return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; - case 13: case 14: + case 13: case 14: case 15: return output_move_vfp (operands); default: gcc_unreachable (); @@ -156,14 +156,15 @@ (const_int 4))] (const_int 4))) (set_attr "type" "*,*,*,load2,store2,*,*,*,*,*,f_mcrr,f_mrrc,\ - ffarithd,f_loadd,f_stored") - (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*") - (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")] + ffarithd,f_loadd,f_loadd,f_stored") + (set_attr "use_literal_pool" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*") + (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,*,1020,*") + (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,*,1008,*")] ) (define_insn "*iwmmxt_movsi_insn" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk, m,z,r,?z,?Uy,*t, r,*t,*t ,*Uv") - (match_operand:SI 1 "general_operand" " rk,I,K,j,mi,rk,r,z,Uy, z, r,*t,*t,*Uvi, *t"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk, m,z,r,?z,?Uy,*t, r,*t,*t, *t, *Uv") + (match_operand:SI 1 "general_operand" " rk,I,K,j,mi,rk,r,z,Uy, z, r,*t,*t,*Uv,*Uvi,*t"))] "TARGET_REALLY_IWMMXT && ( register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" @@ -183,16 +184,17 @@ case 10:return \"fmsr\\t%0, %1\"; case 11:return \"fmrs\\t%0, %1\"; case 12:return \"fcpys\\t%0, %1\\t%@ int\"; - case 13: case 14: + case 13: case 14: case 15: return output_move_vfp (operands); default: gcc_unreachable (); }" [(set_attr "type" "*,*,*,*,load1,store1,*,*,*,*,f_mcr,f_mrc,\ - fmov,f_loads,f_stores") - (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*") - (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*") - (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*") + fmov,f_loads,f_loads,f_stores") + (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*,*") + (set_attr "use_literal_pool" "*,*,*,*,*, *,*,*,*, *,*,*,*,*,yes, *") + (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,*,1008,*") ;; Note - the "predicable" attribute is not allowed to have alternatives. ;; Since the wSTRw wCx instruction is not predicable, we cannot support ;; predicating any of the alternatives in this template. Instead, diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index baeac62..b3017fb 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -22,8 +22,8 @@ ;; ??? For now do not allow loading constants into vfp regs. This causes ;; problems because small constants get converted into adds. (define_insn "*arm_movsi_vfp" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv") - (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *t, *Uv") + (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uv,*Uvi,*t"))] "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT && ( s_register_operand (operands[0], SImode) || s_register_operand (operands[1], SImode))" @@ -46,16 +46,17 @@ return \"vmov%?\\t%0, %1\\t%@ int\"; case 8: return \"vmov%?.f32\\t%0, %1\\t%@ int\"; - case 9: case 10: + case 9: case 10: case 11: return output_move_vfp (operands); default: gcc_unreachable (); } " [(set_attr "predicable" "yes") - (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores") - (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") - (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] + (set_attr "type" "mov_reg,mov_reg,mvn_imm,mov_imm,load1,store1,f_mcr,f_mrc,fmov,f_loads,f_loads,f_stores") + (set_attr "use_literal_pool" "*,*,*,*,*,*,*,*,*,*,yes,*") + (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,*,1020,*") + (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,*,1008,*")] ) ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split @@ -64,8 +65,8 @@ ;; is chosen with length 2 when the instruction is predicated for ;; arm_restrict_it. (define_insn "*thumb2_movsi_vfp" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t, *Uv") - (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t, *t, *Uv") + (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*Uv,*Uvi,*t"))] "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT && ( s_register_operand (operands[0], SImode) || s_register_operand (operands[1], SImode))" @@ -92,26 +93,27 @@ return \"vmov%?\\t%0, %1\\t%@ int\"; case 11: return \"vmov%?.f32\\t%0, %1\\t%@ int\"; - case 12: case 13: + case 12: case 13: case 14: return output_move_vfp (operands); default: gcc_unreachable (); } " [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no") - (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load1,load1,store1,store1,f_mcr,f_mrc,fmov,f_loads,f_stores") - (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4") - (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,1018,*") - (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] + (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no,no,no,no,no,no,no") + (set_attr "type" "mov_reg,mov_reg,mov_reg,mvn_reg,mov_imm,load1,load1,store1,store1,f_mcr,f_mrc,fmov,f_loads,f_loads,f_stores") + (set_attr "length" "2,4,2,4,4,4,4,4,4,4,4,4,4,4,4") + (set_attr "use_literal_pool" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*") + (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*,*,*,*,*,1018,*") + (set_attr "neg_pool_range" "*,*,*,*,*, 0, 0,*,*,*,*,*,*,1008,*")] ) ;; DImode moves (define_insn "*movdi_vfp" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv") - (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))] + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w,w,Uv") + (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uv,Uvi,w"))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode)) @@ -138,13 +140,13 @@ return \"vmov%?.f32\\t%0, %1\\t%@ int\;vmov%?.f32\\t%p0, %p1\\t%@ int\"; else return \"vmov%?.f64\\t%P0, %P1\\t%@ int\"; - case 10: case 11: + case 10: case 11: case 12: return output_move_vfp (operands); default: gcc_unreachable (); } " - [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored") + [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_loadd,f_stored") (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8) (eq_attr "alternative" "2") (const_int 12) (eq_attr "alternative" "3") (const_int 16) @@ -154,15 +156,16 @@ (const_int 8) (const_int 4))] (const_int 4))) - (set_attr "arm_pool_range" "*,*,*,*,1020,4096,*,*,*,*,1020,*") - (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*") - (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*") - (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")] + (set_attr "arm_pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*") + (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,*,1018,*") + (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,*,1004,*") + (set_attr "use_literal_pool" "*,*,*,*,*,*,*,*,*,*,*,yes,*") + (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any,any")] ) (define_insn "*movdi_vfp_cortexa8" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv") - (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w,w,Uv") + (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uv,Uvi,w"))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8 && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode)) @@ -186,13 +189,13 @@ return \"vmov%?\\t%Q0, %R0, %P1\\t%@ int\"; case 9: return \"vmov%?.f64\\t%P0, %P1\\t%@ int\"; - case 10: case 11: + case 10: case 11: case 12: return output_move_vfp (operands); default: gcc_unreachable (); } " - [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored") + [(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_loadd,f_stored") (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8) (eq_attr "alternative" "2") (const_int 12) (eq_attr "alternative" "3") (const_int 16) @@ -202,12 +205,13 @@ * 4")] (const_int 4))) (set_attr "predicable" "yes") - (set_attr "arm_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*") - (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,1018,*") - (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*") + (set_attr "use_literal_pool" "*,*,*,*,*,*,*,*,*,*,*,yes,*") + (set_attr "arm_pool_range" "*,*,*,*,1018,4094,*,*,*,*,*,1018,*") + (set_attr "thumb2_pool_range" "*,*,*,*,1018,4094,*,*,*,*,*,1018,*") + (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,*,1004,*") (set (attr "ce_count") (symbol_ref "get_attr_length (insn) / 4")) - (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")] + (set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any,any")] ) ;; HFmode moves @@ -319,8 +323,8 @@ ;; preferable to loading the value via integer registers. (define_insn "*movsf_vfp" - [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t ,Uv,r ,m,t,r") - (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t, t, Uv,r ,m,t,r") + (match_operand:SF 1 "general_operand" " ?r,t,Dv,Uv,UvE,t, mE,r,t,r"))] "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && ( s_register_operand (operands[0], SFmode) || s_register_operand (operands[1], SFmode))" @@ -333,15 +337,15 @@ return \"vmov%?\\t%0, %1\"; case 2: return \"vmov%?.f32\\t%0, %1\"; - case 3: case 4: + case 3: case 4: case 5: return output_move_vfp (operands); - case 5: - return \"ldr%?\\t%0, %1\\t%@ float\"; case 6: - return \"str%?\\t%1, %0\\t%@ float\"; + return \"ldr%?\\t%0, %1\\t%@ float\"; case 7: - return \"vmov%?.f32\\t%0, %1\"; + return \"str%?\\t%1, %0\\t%@ float\"; case 8: + return \"vmov%?.f32\\t%0, %1\"; + case 9: return \"mov%?\\t%0, %1\\t%@ float\"; default: gcc_unreachable (); @@ -349,14 +353,15 @@ " [(set_attr "predicable" "yes") (set_attr "type" - "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg") - (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") - (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] + "f_mcr,f_mrc,fconsts,f_loads,f_loads,f_stores,load1,store1,fmov,mov_reg") + (set_attr "use_literal_pool" "*,*,*,*,yes,*,*,*,*,*") + (set_attr "pool_range" "*,*,*,*,1020,*,4096,*,*,*") + (set_attr "neg_pool_range" "*,*,*,*,1008,*,4080,*,*,*")] ) (define_insn "*thumb2_movsf_vfp" - [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r") - (match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t, t, Uv,r ,m,t,r") + (match_operand:SF 1 "general_operand" " ?r,t,Dv,Uv,UvE,t, mE,r,t,r"))] "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && ( s_register_operand (operands[0], SFmode) || s_register_operand (operands[1], SFmode))" @@ -369,15 +374,15 @@ return \"vmov%?\\t%0, %1\"; case 2: return \"vmov%?.f32\\t%0, %1\"; - case 3: case 4: + case 3: case 4: case 5: return output_move_vfp (operands); - case 5: - return \"ldr%?\\t%0, %1\\t%@ float\"; case 6: - return \"str%?\\t%1, %0\\t%@ float\"; + return \"ldr%?\\t%0, %1\\t%@ float\"; case 7: - return \"vmov%?.f32\\t%0, %1\"; + return \"str%?\\t%1, %0\\t%@ float\"; case 8: + return \"vmov%?.f32\\t%0, %1\"; + case 9: return \"mov%?\\t%0, %1\\t%@ float\"; default: gcc_unreachable (); @@ -386,16 +391,17 @@ [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" - "f_mcr,f_mrc,fconsts,f_loads,f_stores,load1,store1,fmov,mov_reg") - (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*") - (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] + "f_mcr,f_mrc,fconsts,f_loads,f_loads,f_stores,load1,store1,fmov,mov_reg") + (set_attr "use_literal_pool" "*,*,*,*,yes,*,*,*,*,*") + (set_attr "pool_range" "*,*,*,*,1018,*,4090,*,*,*") + (set_attr "neg_pool_range" "*,*,*,*,1008,*,0,*,*,*")] ) ;; DFmode moves (define_insn "*movdf_vfp" - [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r, m,w,r") - (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w ,mF,r,w,r"))] + [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w, w, Uv,r, m,w,r") + (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,Uv,UvF,w ,mF,r,w,r"))] "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && ( register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" @@ -410,39 +416,40 @@ case 2: gcc_assert (TARGET_VFP_DOUBLE); return \"vmov%?.f64\\t%P0, %1\"; - case 3: case 4: + case 3: case 4: case 5: return output_move_vfp (operands); - case 5: case 6: + case 6: case 7: return output_move_double (operands, true, NULL); - case 7: + case 8: if (TARGET_VFP_SINGLE) return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\"; else return \"vmov%?.f64\\t%P0, %P1\"; - case 8: + case 9: return \"#\"; default: gcc_unreachable (); } } " - [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\ + [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_loadd,f_stored,\ load2,store2,ffarithd,multiple") - (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8) - (eq_attr "alternative" "7") + (set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8) + (eq_attr "alternative" "8") (if_then_else (match_test "TARGET_VFP_SINGLE") (const_int 8) (const_int 4))] (const_int 4))) (set_attr "predicable" "yes") - (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*") - (set_attr "neg_pool_range" "*,*,*,1004,*,1004,*,*,*")] + (set_attr "use_literal_pool" "*,*,*,*,yes,*,*,*,*,*") + (set_attr "pool_range" "*,*,*,*,1020,*,1020,*,*,*") + (set_attr "neg_pool_range" "*,*,*,*,1004,*,1004,*,*,*")] ) (define_insn "*thumb2_movdf_vfp" - [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r ,m,w,r") - (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w, mF,r, w,r"))] + [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w, w, Uv,r ,m,w,r") + (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,Uv,UvF,w, mF,r, w,r"))] "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && ( register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" @@ -457,11 +464,11 @@ case 2: gcc_assert (TARGET_VFP_DOUBLE); return \"vmov%?.f64\\t%P0, %1\"; - case 3: case 4: + case 3: case 4: case 5: return output_move_vfp (operands); - case 5: case 6: case 8: + case 6: case 7: case 9: return output_move_double (operands, true, NULL); - case 7: + case 8: if (TARGET_VFP_SINGLE) return \"vmov%?.f32\\t%0, %1\;vmov%?.f32\\t%p0, %p1\"; else @@ -471,17 +478,18 @@ } } " - [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\ + [(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_loadd,\ f_stored,load2,store2,ffarithd,multiple") - (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8) - (eq_attr "alternative" "7") + (set (attr "length") (cond [(eq_attr "alternative" "6,7,9") (const_int 8) + (eq_attr "alternative" "8") (if_then_else (match_test "TARGET_VFP_SINGLE") (const_int 8) (const_int 4))] (const_int 4))) - (set_attr "pool_range" "*,*,*,1018,*,4094,*,*,*") - (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] + (set_attr "use_literal_pool" "*,*,*,*,yes,*,*,*,*,*") + (set_attr "pool_range" "*,*,*,*,1018,*,4094,*,*,*") + (set_attr "neg_pool_range" "*,*,*,*,1008,*,0,*,*,*")] )