From patchwork Tue Jun 24 22:23:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 363754 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5B94A1400BB for ; Wed, 25 Jun 2014 08:23:56 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type; q=dns; s=default; b=GwpeSNn5fk/z33U0 Xc4PRGfFrII7dOeSGNHtCBlshyVdnxj2FKLNTWsmJAFgG1aoZzzkCVhe33Teyjoz itLmoYhnW2RpCOucf81JdSYgpNCp4ZZtysyGBzY3Y2qwssYPUHKI+bDLt2AySYJZ 3C/JfHNMWt9X49ZpV/gJycAttlQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type; s=default; bh=DnGfE+AX5EHtGooukZvIqO 4Ab5g=; b=kgHu6vCVWrBIleXvOBa59s5S2j7hd6WnMF0ZH4hleOessxAPEglHD0 DUB2CK+BbDsM/JQJC7oBPABrATjWkIopjpvhCzOSlRS3VXUjpD+K1kHinHctvdiq X7K9xZZuq5KwbiBEtHSZVmZNDhq1I4DvG9UxK4dajqyXzA15H2u40= Received: (qmail 1447 invoked by alias); 24 Jun 2014 22:23:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 1437 invoked by uid 89); 24 Jun 2014 22:23:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wg0-f48.google.com Received: from mail-wg0-f48.google.com (HELO mail-wg0-f48.google.com) (74.125.82.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 24 Jun 2014 22:23:46 +0000 Received: by mail-wg0-f48.google.com with SMTP id n12so1026652wgh.19 for ; Tue, 24 Jun 2014 15:23:43 -0700 (PDT) X-Received: by 10.194.84.101 with SMTP id x5mr4991481wjy.52.1403648623144; Tue, 24 Jun 2014 15:23:43 -0700 (PDT) Received: from localhost ([2.26.169.52]) by mx.google.com with ESMTPSA id wz3sm3237221wjc.39.2014.06.24.15.23.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Jun 2014 15:23:42 -0700 (PDT) From: Richard Sandiford To: Matthew Fortune Mail-Followup-To: Matthew Fortune , "'gcc-patches\@gcc.gnu.org' \(gcc-patches\@gcc.gnu.org\)" , Rich Fuhler , Steve Ellcey , rdsandiford@googlemail.com Cc: "'gcc-patches\@gcc.gnu.org' \(gcc-patches\@gcc.gnu.org\)" , Rich Fuhler , Steve Ellcey Subject: Re: [PATCH,MIPS] MIPS64r6 support References: <6D39441BF12EF246A7ABCE6654B023535505A2@LEMAIL01.le.imgtec.org> <87egyrtweg.fsf@talisman.default> <6D39441BF12EF246A7ABCE6654B0235320E11169@LEMAIL01.le.imgtec.org> Date: Tue, 24 Jun 2014 23:23:41 +0100 In-Reply-To: <6D39441BF12EF246A7ABCE6654B0235320E11169@LEMAIL01.le.imgtec.org> (Matthew Fortune's message of "Mon, 23 Jun 2014 10:31:23 +0000") Message-ID: <87pphygd5e.fsf@talisman.default> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Matthew Fortune writes: >> I suppose we'll need a way of specifying an isa_rev range, say >> "isa_rev=2-5". That should be a fairly localised change though. > > There appear to be about 9 tests that are not fixed by educating mips.exp > about flags which are not supported on R6. Steve has initially dealt with > these via forbid_cpu=mips.*r6 but I guess it would be cleaner to try and > support an isa_rev range. I'll see we can club together enough tcl skills > to write it :-) Thanks. I saw the patch Steve posted later, but I'm running out of time to look at it today. Hopefully tomorrow. >> > (if_then_else (match_test "TARGET_MICROMIPS") >> > (match_test "umips_12bit_offset_address_p (op, mode)") >> > - (match_test "mips_address_insns (op, mode, false)"))) >> > + (if_then_else (match_test "ISA_HAS_PREFETCH_9BIT") >> > + (match_test "mipsr6_9bit_offset_address_p (op, mode)") >> > + (match_test "mips_address_insns (op, mode, false)")))) >> >> Please use (cond ...) instead. > > It seems I cannot use cond in a predicate expression, so I've had to > leave it as is. Code outside config/mips can be changed too though. Try the attached. >> > diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h >> > index e539422..751623f 100644 >> > --- a/gcc/config/mips/linux.h >> > +++ b/gcc/config/mips/linux.h >> > @@ -18,8 +18,9 @@ along with GCC; see the file COPYING3. If not see >> > . */ >> > >> > #define GLIBC_DYNAMIC_LINKER \ >> > - "%{mnan=2008:/lib/ld-linux-mipsn8.so.1;:/lib/ld.so.1}" >> > + "%{mnan=2008|mips32r6|mips64r6:/lib/ld-linux- >> mipsn8.so.1;:/lib/ld.so.1}" >> > >> > #undef UCLIBC_DYNAMIC_LINKER >> > #define UCLIBC_DYNAMIC_LINKER \ >> > - "%{mnan=2008:/lib/ld-uClibc-mipsn8.so.0;:/lib/ld-uClibc.so.0}" >> > + "%{mnan=2008|mips32r6|mips64r6:/lib/ld-uClibc-mipsn8.so.0;" \ >> > + ":/lib/ld-uClibc.so.0}" >> >> Rather than update all the specs like this, I think we should force >> -mnan=2008 onto the command line for r6 using DRIVER_SELF_SPECS. >> See e.g. MIPS_ISA_SYNCI_SPEC. > > I agree this could be simpler and your comment has made me realise the > implementation in the patch is wrong for configurations like > mipsisa32r6-unknown-linux-gnu. The issue for both the current patch and > your suggestion is that they rely on MIPS_ISA_LEVEL_SPEC having been > applied but this only happens in the vendor triplets. The --with-arch* > options used with mips-unknown-linux-gnu would be fine as they place > an arch option on the command line. > > If I add MIPS_ISA_LEVEL_SPEC to the DRIVER_SELF_SPECS generic > definition in mips.h then I believe that would fix the problem. Any new > spec I add for R6/nan setting would also need adding to the generic > DRIVER_SELF_SPECS in mips.h and any vendor definitions of > DRIVER_SELF_SPECS. Yeah, sounds like the right way to go. Richard gcc/ * genattrtab.c (check_attr_value): Move COND length check to... * read-rtl.c (read_rtx_code): ...here. * gensupport.c (expand_conds): New function. (process_rtx): Use it on predicate and constraint conditions. Index: gcc/genattrtab.c =================================================================== --- gcc/genattrtab.c 2014-06-24 23:14:49.140002614 +0100 +++ gcc/genattrtab.c 2014-06-24 23:14:49.361004899 +0100 @@ -997,13 +997,6 @@ check_attr_value (rtx exp, struct attr_d break; case COND: - if (XVECLEN (exp, 0) % 2 != 0) - { - error_with_line (attr->lineno, - "first operand of COND must have even length"); - break; - } - for (i = 0; i < XVECLEN (exp, 0); i += 2) { XVECEXP (exp, 0, i) = check_attr_test (XVECEXP (exp, 0, i), Index: gcc/read-rtl.c =================================================================== --- gcc/read-rtl.c 2014-06-24 23:14:49.141002624 +0100 +++ gcc/read-rtl.c 2014-06-24 23:14:49.363004920 +0100 @@ -1350,6 +1350,9 @@ read_rtx_code (const char *code_name) gcc_unreachable (); } + if (code == COND && XVECLEN (return_rtx, 0) % 2 != 0) + fatal_with_file_and_line ("first operand of COND must have even length"); + if (CONST_WIDE_INT_P (return_rtx)) { read_name (&name); Index: gcc/gensupport.c =================================================================== --- gcc/gensupport.c 2014-06-24 23:14:49.140002614 +0100 +++ gcc/gensupport.c 2014-06-24 23:21:35.389211427 +0100 @@ -143,6 +143,44 @@ gen_rtx_CONST_INT (enum machine_mode ARG XWINT (rt, 0) = arg; return rt; } + +/* Expand CONDs in *LOC to IF_THEN_ELSEs. */ + +static void +expand_conds (rtx *loc) +{ + rtx x = *loc; + + if (GET_CODE (x) == COND) + { + *loc = XEXP (x, 1); + for (int i = XVECLEN (x, 0) - 2; i >= 0; i -= 2) + { + rtx cond = rtx_alloc (IF_THEN_ELSE); + XEXP (cond, 0) = XVECEXP (x, 0, i); + XEXP (cond, 1) = XVECEXP (x, 0, i + 1); + XEXP (cond, 2) = *loc; + *loc = cond; + } + x = *loc; + } + + const char *format_ptr = GET_RTX_FORMAT (GET_CODE (x)); + for (int i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) + switch (*format_ptr++) + { + case 'e': + case 'u': + expand_conds (&XEXP (x, i)); + break; + case 'E': + if (XVEC (x, i) != NULL) + for (int j = 0; j < XVECLEN (x, i); j++) + expand_conds (&XVECEXP (x, i, j)); + break; + } +} + /* Predicate handling. @@ -506,13 +544,17 @@ process_rtx (rtx desc, int lineno) case DEFINE_PREDICATE: case DEFINE_SPECIAL_PREDICATE: + expand_conds (&XEXP (desc, 1)); process_define_predicate (desc, lineno); - /* Fall through. */ + queue_pattern (desc, &define_pred_tail, read_md_filename, lineno); + break; case DEFINE_CONSTRAINT: - case DEFINE_REGISTER_CONSTRAINT: case DEFINE_MEMORY_CONSTRAINT: case DEFINE_ADDRESS_CONSTRAINT: + expand_conds (&XEXP (desc, 2)); + /* Fall through. */ + case DEFINE_REGISTER_CONSTRAINT: queue_pattern (desc, &define_pred_tail, read_md_filename, lineno); break;