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[188.29.164.51]) by smtp.gmail.com with ESMTPSA id e77sm1770477wmi.16.2017.10.27.06.26.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 27 Oct 2017 06:26:02 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, richard.sandiford@linaro.org Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [04/nn] [AArch64] Rename the internal "Upl" constraint References: <873764d8y3.fsf@linaro.org> Date: Fri, 27 Oct 2017 14:25:56 +0100 In-Reply-To: <873764d8y3.fsf@linaro.org> (Richard Sandiford's message of "Fri, 27 Oct 2017 14:19:48 +0100") Message-ID: <87inf0bu3f.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 The SVE port uses the public constraints "Upl" and "Upa" to mean "low predicate register" and "any predicate register" respectively. "Upl" was already used as an internal-only constraint by the addition patterns, so this patch renames it to "Uaa" ("two adds needed"). 2017-10-27 Richard Sandiford Alan Hayward David Sherwood gcc/ * config/aarch64/constraints.md (Upl): Rename to... (Uaa): ...this. * config/aarch64/aarch64.md (*zero_extend2_aarch64, *addsi3_aarch64_uxtw): Update accordingly. Reviewed-By: James Greenhalgh Index: gcc/config/aarch64/constraints.md =================================================================== --- gcc/config/aarch64/constraints.md 2017-10-27 14:06:16.159815485 +0100 +++ gcc/config/aarch64/constraints.md 2017-10-27 14:11:54.071011147 +0100 @@ -35,7 +35,7 @@ (define_constraint "I" (and (match_code "const_int") (match_test "aarch64_uimm12_shift (ival)"))) -(define_constraint "Upl" +(define_constraint "Uaa" "@internal A constant that matches two uses of add instructions." (and (match_code "const_int") (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)"))) Index: gcc/config/aarch64/aarch64.md =================================================================== --- gcc/config/aarch64/aarch64.md 2017-10-27 14:07:01.875769946 +0100 +++ gcc/config/aarch64/aarch64.md 2017-10-27 14:11:54.071011147 +0100 @@ -1562,7 +1562,7 @@ (define_insn "*add3_aarch64" (match_operand:GPI 0 "register_operand" "=rk,rk,w,rk,r") (plus:GPI (match_operand:GPI 1 "register_operand" "%rk,rk,w,rk,rk") - (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Upl")))] + (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Uaa")))] "" "@ add\\t%0, %1, %2 @@ -1580,7 +1580,7 @@ (define_insn "*addsi3_aarch64_uxtw" (match_operand:DI 0 "register_operand" "=rk,rk,rk,r") (zero_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk,rk") - (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Upl"))))] + (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Uaa"))))] "" "@ add\\t%w0, %w1, %2