diff mbox series

amdgcn: additional gfx1030/gfx1100 support: adjust test cases (was: [PATCH] amdgcn: additional gfx1100 support)

Message ID 87edcnjwrn.fsf@euler.schwinge.ddns.net
State New
Headers show
Series amdgcn: additional gfx1030/gfx1100 support: adjust test cases (was: [PATCH] amdgcn: additional gfx1100 support) | expand

Commit Message

Thomas Schwinge March 6, 2024, 1:49 p.m. UTC 
Hi!

On 2024-01-24T12:43:04+0000, Andrew Stubbs <ams@baylibre.com> wrote:
> This [...]

... became commit 99890e15527f1f04caef95ecdd135c9f1a077f08
"amdgcn: additional gfx1030/gfx1100 support", and included the following:

> --- a/gcc/config/gcn/gcn-valu.md
> +++ b/gcc/config/gcn/gcn-valu.md
> @@ -3555,30 +3555,63 @@
>  ;; }}}
>  ;; {{{ Int/int conversions
>  
> +(define_code_iterator all_convert [truncate zero_extend sign_extend])
>  (define_code_iterator zero_convert [truncate zero_extend])
>  (define_code_attr convop [
>  	(sign_extend "extend")
>  	(zero_extend "zero_extend")
>  	(truncate "trunc")])
>  
> -(define_insn "<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>"
> +(define_expand "<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>"
> +  [(set (match_operand:V_INT_1REG 0 "register_operand"      "=v")
> +        (all_convert:V_INT_1REG
> +	  (match_operand:V_INT_1REG_ALT 1 "gcn_alu_operand" " v")))]
> +  "")
> +
> +(define_insn "*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>"
>    [(set (match_operand:V_INT_1REG 0 "register_operand"      "=v")
>          (zero_convert:V_INT_1REG
>  	  (match_operand:V_INT_1REG_ALT 1 "gcn_alu_operand" " v")))]
> -  ""
> +  "!TARGET_RDNA3"
>    "v_mov_b32_sdwa\t%0, %1 dst_sel:<V_INT_1REG:sdwa> dst_unused:UNUSED_PAD src0_sel:<V_INT_1REG_ALT:sdwa>"
>    [(set_attr "type" "vop_sdwa")
>     (set_attr "length" "8")])
>  
> -(define_insn "extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>"
> +(define_insn "extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>"
>    [(set (match_operand:V_INT_1REG 0 "register_operand"	    "=v")
>          (sign_extend:V_INT_1REG
>  	  (match_operand:V_INT_1REG_ALT 1 "gcn_alu_operand" " v")))]
> -  ""
> +  "!TARGET_RDNA3"
>    "v_mov_b32_sdwa\t%0, sext(%1) src0_sel:<V_INT_1REG_ALT:sdwa>"
>    [(set_attr "type" "vop_sdwa")
>     (set_attr "length" "8")])
>  
> +(define_insn "*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>"
> +  [(set (match_operand:V_INT_1REG 0 "register_operand"      "=v")
> +        (all_convert:V_INT_1REG
> +	  (match_operand:V_INT_1REG_ALT 1 "gcn_alu_operand" " v")))]
> +  "TARGET_RDNA3"
> +  {
> +    enum {extend, zero_extend, trunc};
> +    rtx shiftwidth = (<V_INT_1REG_ALT:SCALAR_MODE>mode == QImode
> +		      || <V_INT_1REG:SCALAR_MODE>mode == QImode
> +		      ? GEN_INT (24)
> +		      : <V_INT_1REG_ALT:SCALAR_MODE>mode == HImode
> +		        || <V_INT_1REG:SCALAR_MODE>mode == HImode
> +		      ? GEN_INT (16)
> +		      : NULL);
> +    operands[2] = shiftwidth;
> +
> +    if (!shiftwidth)
> +      return "v_mov_b32 %0, %1";
> +    else if (<convop> == extend || <convop> == trunc)
> +      return "v_lshlrev_b32\t%0, %2, %1\;v_ashrrev_i32\t%0, %2, %0";
> +    else
> +      return "v_lshlrev_b32\t%0, %2, %1\;v_lshrrev_b32\t%0, %2, %0";
> +  }
> +  [(set_attr "type" "mult")
> +   (set_attr "length" "8")])

OK to push the attached
"amdgcn: additional gfx1030/gfx1100 support: adjust test cases"?
Tested 'gcn.exp' for all '-march'es.


Grüße
 Thomas

Comments

Andrew Stubbs March 6, 2024, 2:03 p.m. UTC | #1 
On 06/03/2024 13:49, Thomas Schwinge wrote:
> Hi!
> 
> On 2024-01-24T12:43:04+0000, Andrew Stubbs <ams@baylibre.com> wrote:
>> This [...]
> 
> ... became commit 99890e15527f1f04caef95ecdd135c9f1a077f08
> "amdgcn: additional gfx1030/gfx1100 support", and included the following:
> 
>> --- a/gcc/config/gcn/gcn-valu.md
>> +++ b/gcc/config/gcn/gcn-valu.md
>> @@ -3555,30 +3555,63 @@
>>   ;; }}}
>>   ;; {{{ Int/int conversions
>>   
>> +(define_code_iterator all_convert [truncate zero_extend sign_extend])
>>   (define_code_iterator zero_convert [truncate zero_extend])
>>   (define_code_attr convop [
>>   	(sign_extend "extend")
>>   	(zero_extend "zero_extend")
>>   	(truncate "trunc")])
>>   
>> -(define_insn "<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>"
>> +(define_expand "<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>"
>> +  [(set (match_operand:V_INT_1REG 0 "register_operand"      "=v")
>> +        (all_convert:V_INT_1REG
>> +	  (match_operand:V_INT_1REG_ALT 1 "gcn_alu_operand" " v")))]
>> +  "")
>> +
>> +(define_insn "*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>"
>>     [(set (match_operand:V_INT_1REG 0 "register_operand"      "=v")
>>           (zero_convert:V_INT_1REG
>>   	  (match_operand:V_INT_1REG_ALT 1 "gcn_alu_operand" " v")))]
>> -  ""
>> +  "!TARGET_RDNA3"
>>     "v_mov_b32_sdwa\t%0, %1 dst_sel:<V_INT_1REG:sdwa> dst_unused:UNUSED_PAD src0_sel:<V_INT_1REG_ALT:sdwa>"
>>     [(set_attr "type" "vop_sdwa")
>>      (set_attr "length" "8")])
>>   
>> -(define_insn "extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>"
>> +(define_insn "extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>"
>>     [(set (match_operand:V_INT_1REG 0 "register_operand"	    "=v")
>>           (sign_extend:V_INT_1REG
>>   	  (match_operand:V_INT_1REG_ALT 1 "gcn_alu_operand" " v")))]
>> -  ""
>> +  "!TARGET_RDNA3"
>>     "v_mov_b32_sdwa\t%0, sext(%1) src0_sel:<V_INT_1REG_ALT:sdwa>"
>>     [(set_attr "type" "vop_sdwa")
>>      (set_attr "length" "8")])
>>   
>> +(define_insn "*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>"
>> +  [(set (match_operand:V_INT_1REG 0 "register_operand"      "=v")
>> +        (all_convert:V_INT_1REG
>> +	  (match_operand:V_INT_1REG_ALT 1 "gcn_alu_operand" " v")))]
>> +  "TARGET_RDNA3"
>> +  {
>> +    enum {extend, zero_extend, trunc};
>> +    rtx shiftwidth = (<V_INT_1REG_ALT:SCALAR_MODE>mode == QImode
>> +		      || <V_INT_1REG:SCALAR_MODE>mode == QImode
>> +		      ? GEN_INT (24)
>> +		      : <V_INT_1REG_ALT:SCALAR_MODE>mode == HImode
>> +		        || <V_INT_1REG:SCALAR_MODE>mode == HImode
>> +		      ? GEN_INT (16)
>> +		      : NULL);
>> +    operands[2] = shiftwidth;
>> +
>> +    if (!shiftwidth)
>> +      return "v_mov_b32 %0, %1";
>> +    else if (<convop> == extend || <convop> == trunc)
>> +      return "v_lshlrev_b32\t%0, %2, %1\;v_ashrrev_i32\t%0, %2, %0";
>> +    else
>> +      return "v_lshlrev_b32\t%0, %2, %1\;v_lshrrev_b32\t%0, %2, %0";
>> +  }
>> +  [(set_attr "type" "mult")
>> +   (set_attr "length" "8")])
> 
> OK to push the attached
> "amdgcn: additional gfx1030/gfx1100 support: adjust test cases"?
> Tested 'gcn.exp' for all '-march'es.

LGTM.

Andrew
diff mbox series

Patch

From 04b83e9aa19b02b9805e03f31db14325bb00e737 Mon Sep 17 00:00:00 2001
From: Thomas Schwinge <tschwinge@baylibre.com>
Date: Mon, 4 Mar 2024 10:40:39 +0100
Subject: [PATCH] amdgcn: additional gfx1030/gfx1100 support: adjust test cases

The "SDWA" changes in commit 99890e15527f1f04caef95ecdd135c9f1a077f08
"amdgcn: additional gfx1030/gfx1100 support" caused a few regressions:

    PASS: gcc.target/gcn/sram-ecc-3.c (test for excess errors)
    [-PASS:-]{+FAIL:+} gcc.target/gcn/sram-ecc-3.c scan-assembler zero_extendv64qiv64si2

    PASS: gcc.target/gcn/sram-ecc-4.c (test for excess errors)
    [-PASS:-]{+FAIL:+} gcc.target/gcn/sram-ecc-4.c scan-assembler zero_extendv64hiv64si2

    PASS: gcc.target/gcn/sram-ecc-7.c (test for excess errors)
    [-PASS:-]{+FAIL:+} gcc.target/gcn/sram-ecc-7.c scan-assembler zero_extendv64qiv64si2

    PASS: gcc.target/gcn/sram-ecc-8.c (test for excess errors)
    [-PASS:-]{+FAIL:+} gcc.target/gcn/sram-ecc-8.c scan-assembler zero_extendv64hiv64si2

Those test cases need corresponding adjustment.

	gcc/testsuite/
	* gcc.target/gcn/sram-ecc-3.c: Adjust.
	* gcc.target/gcn/sram-ecc-4.c: Likewise.
	* gcc.target/gcn/sram-ecc-7.c: Likewise.
	* gcc.target/gcn/sram-ecc-8.c: Likewise.
---
 gcc/testsuite/gcc.target/gcn/sram-ecc-3.c | 2 +-
 gcc/testsuite/gcc.target/gcn/sram-ecc-4.c | 2 +-
 gcc/testsuite/gcc.target/gcn/sram-ecc-7.c | 2 +-
 gcc/testsuite/gcc.target/gcn/sram-ecc-8.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c
index 692d4578b66..bc89e3542d2 100644
--- a/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c
+++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c
@@ -18,4 +18,4 @@  f ()
     a[n] = b[n];
 }
 
-/* { dg-final { scan-assembler "zero_extendv64qiv64si2" } } */
+/* { dg-final { scan-assembler "(\\\*zero_extendv64qiv64si_sdwa|\\\*zero_extendv64qiv64si_shift)" } } */
diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c
index 61b8d552759..ff7e2d0bda5 100644
--- a/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c
+++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c
@@ -18,4 +18,4 @@  f ()
     a[n] = b[n];
 }
 
-/* { dg-final { scan-assembler "zero_extendv64hiv64si2" } } */
+/* { dg-final { scan-assembler "(\\\*zero_extendv64hiv64si_sdwa|\\\*zero_extendv64hiv64si_shift)" } } */
diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c
index 9d0ce6f6b5a..8d363970ffb 100644
--- a/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c
+++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c
@@ -18,4 +18,4 @@  f ()
     a[n] = b[n];
 }
 
-/* { dg-final { scan-assembler "zero_extendv64qiv64si2" } } */
+/* { dg-final { scan-assembler "(\\\*zero_extendv64qiv64si_sdwa|\\\*zero_extendv64qiv64si_shift)" } } */
diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c
index 76e02882798..a2b25076ed1 100644
--- a/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c
+++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c
@@ -18,4 +18,4 @@  f ()
     a[n] = b[n];
 }
 
-/* { dg-final { scan-assembler "zero_extendv64hiv64si2" } } */
+/* { dg-final { scan-assembler "(\\\*zero_extendv64hiv64si_sdwa|\\\*zero_extendv64hiv64si_shift)" } } */
-- 
2.34.1