From patchwork Thu Jan 14 12:37:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Clifton X-Patchwork-Id: 567366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AAA5614031E for ; Thu, 14 Jan 2016 23:37:29 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=uTiOB5Fx; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=HLMJqB0xEaOwSFvaVMeO84HcafgWojHmvA7YmrlQak7Cec4I8gnm8 vPe8cvhN8cgDXnlYnAeopHQYbIj9GgSR/ZwWR4qBlzgX3MMFl/7zxdC5nBMxhmGC aKILW8QX/YHKhKR9Dx838mjDnD9JQBGBZESPhvumjtuiRAzNelcse0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=+AnDB3hQ2az7sGsWn92I4jkupDI=; b=uTiOB5FxbD00WA1uLY0A Nf5Hp400VmVs92nEiVz1TWlmIPEuK2ql+L08X69dH59I5CRTIVyTXkVSQDuUm2Yr NAAaQVSyWMgVgtp65dzVoIICpvWMPyttLP/2+4HqO15/yaJpujCiGUiVZ/zJ6UN0 Kx/9fQZkQa52N9MmxsL0WXA= Received: (qmail 50805 invoked by alias); 14 Jan 2016 12:37:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 50794 invoked by uid 89); 14 Jan 2016 12:37:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=BAYES_00, KAM_ASCII_DIVIDERS, RP_MATCHES_RCVD, SPF_HELO_PASS autolearn=no version=3.3.2 spammy=whilst, pr69180.c, pr69180c, UD:pr69180.c X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Thu, 14 Jan 2016 12:37:21 +0000 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (Postfix) with ESMTPS id CCEF53CA17A for ; Thu, 14 Jan 2016 12:37:19 +0000 (UTC) Received: from littlehelper.redhat.com (vpn1-5-10.ams2.redhat.com [10.36.5.10]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u0ECbEhF025591 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO) for ; Thu, 14 Jan 2016 07:37:15 -0500 From: Nick Clifton To: gcc-patches@gcc.gnu.org Subject: Commit: Try harder to run ARM neon testcases Date: Thu, 14 Jan 2016 12:37:14 +0000 Message-ID: <8737u0qqv9.fsf@redhat.com> MIME-Version: 1.0 X-IsSubscribed: yes Hi Guys Whilst checking PR 69194 I noticed that the new testcase (gcc.target/arm/pr69194.c) was not being run with a Linux hosted toolchain configured as --target=arm-eabi. Investigating further I found that the check_effective_target_arm_neon_ok_nocache proc in target_supports.exp was returning false because the default ARM architecture was v4 not v7. So I am applying the patch below which adds a command line option sequence involving -march=armv7-a to the list of combinations to try in check_effective_target_arm_neon_ok_nocache. Whilst checking this part of the patch I found several ARM tests that check for arm_neon_ok but then do not use the option sequence discovered, so I have updated those as well. The result - the number of unsupported tests drops by 48 and the number of passes increases by 115 for each ARM multilib tested. Plus there are no regressions or new, unexpected failures. Cheers Nick gcc/testsuite/ChangeLog 2016-01-14 Nick Clifton * lib/target-supports.exp (check_effective_target_arm_neon_ok_nocache): Add an option sequence that includes setting the ARM architecture to ARMv7-A. * gcc.target/arm/attr-neon.c: Use dg-add-options to add the command line options necessary to enable Neon support. * gcc.target/arm/neon-vlshr-imm-1.c: Likewise. * gcc.target/arm/neon-vshl-imm-1.c: Likewise. * gcc.target/arm/neon-vshr-imm-1.c: Likewise. * gcc.target/arm/pr69180.c: Likewise. Index: gcc/testsuite/gcc.target/arm/attr-neon.c =================================================================== --- gcc/testsuite/gcc.target/arm/attr-neon.c (revision 232361) +++ gcc/testsuite/gcc.target/arm/attr-neon.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-O2 -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ /* Verify that neon instructions are emitted once. */ void __attribute__ ((target("fpu=neon"))) Index: gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c =================================================================== --- gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c (revision 232361) +++ gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ /* { dg-final { scan-assembler "vshr\.u32.*#3" } } */ /* Verify that VSHR immediate is used. */ Index: gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c =================================================================== --- gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c (revision 232361) +++ gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ /* { dg-final { scan-assembler "vshl\.i32.*#3" } } */ /* Verify that VSHR immediate is used. */ Index: gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c =================================================================== --- gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c (revision 232361) +++ gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ /* { dg-final { scan-assembler "vshr\.s32.*#3" } } */ /* Verify that VSHR immediate is used. */ Index: gcc/testsuite/gcc.target/arm/pr69180.c =================================================================== --- gcc/testsuite/gcc.target/arm/pr69180.c (revision 232361) +++ gcc/testsuite/gcc.target/arm/pr69180.c (working copy) @@ -3,8 +3,8 @@ #pragma GCC target. */ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-mfloat-abi=softfp -mfpu=neon" } */ - +/* { dg-options " " } */ /* Necessary to prevent the harness from adding -ansi -pedantic-errors to the command line. */ +/* { dg-add-options arm_neon } */ #pragma GCC target ("fpu=neon-fp-armv8") #define __ARM_NEON_FP 0 Index: gcc/testsuite/lib/target-supports.exp =================================================================== --- gcc/testsuite/lib/target-supports.exp (revision 232361) +++ gcc/testsuite/lib/target-supports.exp (working copy) @@ -2888,7 +2888,7 @@ global et_arm_neon_flags set et_arm_neon_flags "" if { [check_effective_target_arm32] } { - foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp"} { + foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp" "-mfpu=neon -mfloat-abi=softfp -march=armv7-a"} { if { [check_no_compiler_messages_nocache arm_neon_ok object { int dummy; #ifndef __ARM_NEON__