| Message ID | 8737u0qqv9.fsf@redhat.com |
|---|---|
| State | New |
| Headers | show |
On 01/14/2016 01:37 PM, Nick Clifton wrote: > Hi Guys > > Whilst checking PR 69194 I noticed that the new testcase > (gcc.target/arm/pr69194.c) was not being run with a Linux hosted > toolchain configured as --target=arm-eabi. Investigating further I > found that the check_effective_target_arm_neon_ok_nocache proc in > target_supports.exp was returning false because the default ARM > architecture was v4 not v7. > > So I am applying the patch below which adds a command line option > sequence involving -march=armv7-a to the list of combinations to try > in check_effective_target_arm_neon_ok_nocache. Whilst checking this > part of the patch I found several ARM tests that check for arm_neon_ok > but then do not use the option sequence discovered, so I have updated > those as well. good step. indeed it looks like that many tests are sometimes conservatively unsupported > The result - the number of unsupported tests drops by 48 and the > number of passes increases by 115 for each ARM multilib tested. Plus > there are no regressions or new, unexpected failures. > > Cheers > Nick > > gcc/testsuite/ChangeLog > 2016-01-14 Nick Clifton <nickc@redhat.com> > > * lib/target-supports.exp > (check_effective_target_arm_neon_ok_nocache): Add an option > sequence that includes setting the ARM architecture to ARMv7-A. > * gcc.target/arm/attr-neon.c: Use dg-add-options to add the > command line options necessary to enable Neon support. is this last one needed ? the __attribute__ ((target("fpu=neon"))) is here to test without -mfpu=neon. So we are losing something here. thanks > * gcc.target/arm/neon-vlshr-imm-1.c: Likewise. > * gcc.target/arm/neon-vshl-imm-1.c: Likewise. > * gcc.target/arm/neon-vshr-imm-1.c: Likewise. > * gcc.target/arm/pr69180.c: Likewise. >
Index: gcc/testsuite/gcc.target/arm/attr-neon.c =================================================================== --- gcc/testsuite/gcc.target/arm/attr-neon.c (revision 232361) +++ gcc/testsuite/gcc.target/arm/attr-neon.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-O2 -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ /* Verify that neon instructions are emitted once. */ void __attribute__ ((target("fpu=neon"))) Index: gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c =================================================================== --- gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c (revision 232361) +++ gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ /* { dg-final { scan-assembler "vshr\.u32.*#3" } } */ /* Verify that VSHR immediate is used. */ Index: gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c =================================================================== --- gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c (revision 232361) +++ gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ /* { dg-final { scan-assembler "vshl\.i32.*#3" } } */ /* Verify that VSHR immediate is used. */ Index: gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c =================================================================== --- gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c (revision 232361) +++ gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ +/* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ /* { dg-final { scan-assembler "vshr\.s32.*#3" } } */ /* Verify that VSHR immediate is used. */ Index: gcc/testsuite/gcc.target/arm/pr69180.c =================================================================== --- gcc/testsuite/gcc.target/arm/pr69180.c (revision 232361) +++ gcc/testsuite/gcc.target/arm/pr69180.c (working copy) @@ -3,8 +3,8 @@ #pragma GCC target. */ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-mfloat-abi=softfp -mfpu=neon" } */ - +/* { dg-options " " } */ /* Necessary to prevent the harness from adding -ansi -pedantic-errors to the command line. */ +/* { dg-add-options arm_neon } */ #pragma GCC target ("fpu=neon-fp-armv8") #define __ARM_NEON_FP 0 Index: gcc/testsuite/lib/target-supports.exp =================================================================== --- gcc/testsuite/lib/target-supports.exp (revision 232361) +++ gcc/testsuite/lib/target-supports.exp (working copy) @@ -2888,7 +2888,7 @@ global et_arm_neon_flags set et_arm_neon_flags "" if { [check_effective_target_arm32] } { - foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp"} { + foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp" "-mfpu=neon -mfloat-abi=softfp -march=armv7-a"} { if { [check_no_compiler_messages_nocache arm_neon_ok object { int dummy; #ifndef __ARM_NEON__