From patchwork Sun Oct 2 17:45:42 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 117355 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 892C81007D6 for ; Mon, 3 Oct 2011 04:46:08 +1100 (EST) Received: (qmail 13373 invoked by alias); 2 Oct 2011 17:46:06 -0000 Received: (qmail 13365 invoked by uid 22791); 2 Oct 2011 17:46:05 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-wy0-f175.google.com (HELO mail-wy0-f175.google.com) (74.125.82.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 02 Oct 2011 17:45:51 +0000 Received: by wyh5 with SMTP id 5so2768627wyh.20 for ; Sun, 02 Oct 2011 10:45:49 -0700 (PDT) Received: by 10.227.20.67 with SMTP id e3mr2045855wbb.5.1317577549051; Sun, 02 Oct 2011 10:45:49 -0700 (PDT) Received: from localhost (rsandifo.gotadsl.co.uk. [82.133.89.107]) by mx.google.com with ESMTPS id es10sm19338085wbb.4.2011.10.02.10.45.46 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 02 Oct 2011 10:45:47 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, rdsandiford@googlemail.com Subject: [committed, MIPS] Fix PR 49696 Date: Sun, 02 Oct 2011 18:45:42 +0100 Message-ID: <871uuv8eyh.fsf@firetop.home> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.2 (gnu/linux) MIME-Version: 1.0 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org PR 49969 showed a mismatch between the short sync expanders and their associated insns: the former allowed zero operands but the predicates in the latter didn't. Tested on mips64-linux-gnu and applied. Richard gcc/ PR target/49696 * config/mips/sync.md (sync__12): Allow zero operands. (sync_old__12, sync_new__12, sync_nand_12): Likewise. (sync_old_nand_12, sync_new_nand_12, test_and_set_12): Likewise. gcc/testsuite/ * gcc.dg/pr49696.c: New test. Index: gcc/config/mips/sync.md =================================================================== --- gcc/config/mips/sync.md 2011-10-02 18:40:01.000000000 +0100 +++ gcc/config/mips/sync.md 2011-10-02 18:42:25.000000000 +0100 @@ -136,7 +136,7 @@ (define_insn "sync__12" [(match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d") (atomic_hiqi_op:SI (match_dup 0) - (match_operand:SI 3 "register_operand" "dJ"))] + (match_operand:SI 3 "reg_or_0_operand" "dJ"))] UNSPEC_SYNC_OLD_OP_12)) (clobber (match_scratch:SI 4 "=&d"))] "GENERATE_LL_SC" @@ -177,7 +177,7 @@ (define_insn "sync_old__12" [(match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d") (atomic_hiqi_op:SI (match_dup 0) - (match_operand:SI 4 "register_operand" "dJ"))] + (match_operand:SI 4 "reg_or_0_operand" "dJ"))] UNSPEC_SYNC_OLD_OP_12)) (clobber (match_scratch:SI 5 "=&d"))] "GENERATE_LL_SC" @@ -218,7 +218,7 @@ (define_insn "sync_new__12" (match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d") (atomic_hiqi_op:SI (match_dup 0) - (match_operand:SI 4 "register_operand" "dJ"))] + (match_operand:SI 4 "reg_or_0_operand" "dJ"))] UNSPEC_SYNC_NEW_OP_12)) (set (match_dup 1) (unspec_volatile:SI @@ -259,7 +259,7 @@ (define_insn "sync_nand_12" [(match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d") (match_dup 0) - (match_operand:SI 3 "register_operand" "dJ")] + (match_operand:SI 3 "reg_or_0_operand" "dJ")] UNSPEC_SYNC_OLD_OP_12)) (clobber (match_scratch:SI 4 "=&d"))] "GENERATE_LL_SC" @@ -298,7 +298,7 @@ (define_insn "sync_old_nand_12" (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d") - (match_operand:SI 4 "register_operand" "dJ")] + (match_operand:SI 4 "reg_or_0_operand" "dJ")] UNSPEC_SYNC_OLD_OP_12)) (clobber (match_scratch:SI 5 "=&d"))] "GENERATE_LL_SC" @@ -337,7 +337,7 @@ (define_insn "sync_new_nand_12" [(match_operand:SI 1 "memory_operand" "+R") (match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d") - (match_operand:SI 4 "register_operand" "dJ")] + (match_operand:SI 4 "reg_or_0_operand" "dJ")] UNSPEC_SYNC_NEW_OP_12)) (set (match_dup 1) (unspec_volatile:SI @@ -546,7 +546,7 @@ (define_insn "test_and_set_12" (set (match_dup 1) (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d") - (match_operand:SI 4 "arith_operand" "dJ")] + (match_operand:SI 4 "reg_or_0_operand" "dJ")] UNSPEC_SYNC_EXCHANGE_12))] "GENERATE_LL_SC" { return mips_output_sync_loop (insn, operands); } Index: gcc/testsuite/gcc.dg/pr49696.c =================================================================== --- /dev/null 2011-10-02 10:31:49.966695399 +0100 +++ gcc/testsuite/gcc.dg/pr49696.c 2011-10-02 18:42:25.000000000 +0100 @@ -0,0 +1,29 @@ +/* { dg-require-effective-target sync_char_short } */ + +/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */ + +void +foo (short *x) +{ + __sync_val_compare_and_swap (x, 1, 0); + __sync_bool_compare_and_swap (x, 1, 0); + __sync_lock_test_and_set (x, 0); + + __sync_fetch_and_add (x, 0); + __sync_fetch_and_add (x, 0); + __sync_fetch_and_add (x, 0); + __sync_fetch_and_sub (x, 0); + __sync_fetch_and_and (x, 0); + __sync_fetch_and_or (x, 0); + __sync_fetch_and_xor (x, 0); + __sync_fetch_and_nand (x, 0); + + __sync_add_and_fetch (x, 0); + __sync_add_and_fetch (x, 0); + __sync_add_and_fetch (x, 0); + __sync_sub_and_fetch (x, 0); + __sync_and_and_fetch (x, 0); + __sync_or_and_fetch (x, 0); + __sync_xor_and_fetch (x, 0); + __sync_nand_and_fetch (x, 0); +}