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[sh] Avoid genrecog warning

Message ID 871u286dv2.fsf@talisman.default
State New
Headers show

Commit Message

Richard Sandiford Nov. 22, 2013, 8:26 a.m. UTC 
I have a patch to upgrade most genrecog warnings into errors.  This patch
fixes the ones for sh.  There were some warnings about the match_operands
in some define_peephole2s having constraints.  There were also a few
cases where a destination predicate allowed a constant.

Tested by building sh-elf with the warnings turned to errors, and by
comparing the before and after assembly output at -O2 for gcc.c-torture,
gcc.dg and g++.dg.  OK to install?

Thanks,
Richard


gcc/
	* config/sh/sh.md: Use nonimmediate_operand rather than general_operand
	for the destination of a define_peephole2.  Likewise register_operand
	rather than arith_reg_operand.  Remove constraints from
	define_peephole2s.

Comments

Kaz Kojima Nov. 23, 2013, 12:01 a.m. UTC | #1 
Richard Sandiford <rdsandiford@googlemail.com> wrote:
> I have a patch to upgrade most genrecog warnings into errors.  This patch
> fixes the ones for sh.  There were some warnings about the match_operands
> in some define_peephole2s having constraints.  There were also a few
> cases where a destination predicate allowed a constant.
> 
> Tested by building sh-elf with the warnings turned to errors, and by
> comparing the before and after assembly output at -O2 for gcc.c-torture,
> gcc.dg and g++.dg.  OK to install?

OK.  Thanks!

Regards,
	kaz
diff mbox

Patch

Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	2013-11-16 21:52:15.083787117 +0000
+++ gcc/config/sh/sh.md	2013-11-16 21:59:05.056092176 +0000
@@ -6065,7 +6065,7 @@  (define_insn "*zero_extend<mode>si2_disp
 (define_peephole2
   [(set (match_operand:SI 0 "arith_reg_dest" "")
 	(zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
-   (set (match_operand 2 "general_operand" "")
+   (set (match_operand 2 "nonimmediate_operand" "")
 	(match_operand 3 "arith_reg_operand" ""))]
   "TARGET_SH2A
    && REGNO (operands[0]) == REGNO (operands[3])
@@ -13700,13 +13700,13 @@  (define_insn "bxorreg_m2a"
 ;; -------------------------------------------------------------------------
 ;; This matches cases where the bit in a memory location is set.
 (define_peephole2
-  [(set (match_operand:SI 0 "arith_reg_operand" "r,r")
-	(sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")))
+  [(set (match_operand:SI 0 "register_operand")
+	(sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
    (set (match_dup 0)
 	(ior:SI (match_dup 0)
-	(match_operand:SI 2 "const_int_operand" "Pso,Pso")))
+	(match_operand:SI 2 "const_int_operand")))
    (set (match_dup 1)
-	(match_operand 3 "arith_reg_operand" "r,r"))]
+	(match_operand 3 "arith_reg_operand"))]
   "TARGET_SH2A && TARGET_BITOPS
    && satisfies_constraint_Pso (operands[2])
    && REGNO (operands[0]) == REGNO (operands[3])"
@@ -13716,13 +13716,13 @@  (define_peephole2
 
 ;; This matches cases where the bit in a memory location is cleared.
 (define_peephole2
-  [(set (match_operand:SI 0 "arith_reg_operand" "r,r")
-	(sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")))
+  [(set (match_operand:SI 0 "register_operand")
+	(sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
    (set (match_dup 0)
 	(and:SI (match_dup 0)
-	(match_operand:SI 2 "const_int_operand" "Psz,Psz")))
+	(match_operand:SI 2 "const_int_operand")))
    (set (match_dup 1)
-	(match_operand 3 "arith_reg_operand" "r,r"))]
+	(match_operand 3 "arith_reg_operand"))]
   "TARGET_SH2A && TARGET_BITOPS
    && satisfies_constraint_Psz (operands[2])
    && REGNO (operands[0]) == REGNO (operands[3])"