From patchwork Fri Jan 10 12:23:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 1221041 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-517088-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=ZVYH/iIC; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47vMb505F7z9sRQ for ; Fri, 10 Jan 2020 23:23:25 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=nqBRz+b3+lw0a0diSQHP+oex5GL+uIXX9DIErulrMdU+uvmaqm BVP9MQD/72wFOba1QJugvp40BZqg3ti3+wVV9Hpgx75+Tx231rq7UzATInnTIJsW qoUsHE3siJ1wu/azxjnpKVWEYgDfwD6kH1wZCDbUTHfwBpGoZmSiqOuuQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=pfwfnDdeMxspWln+KB+3Bl3ph30=; b=ZVYH/iIC5lpxSAMENLgJ Of0f8cfWfDBNfdDx7x9GX+HzjshwE3eOASdW/6tqMYlgsHjqloMZe5KOrxONHlWX B4Fv+KDRiT38Z5YXpe301xwuLopxb5t6vawep7LEgCOudvFb6EQhR/BhVOh0VCJb s/Y6crdNWzwCdeVWmgWo0f0= Received: (qmail 121934 invoked by alias); 10 Jan 2020 12:23:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 121924 invoked by uid 89); 10 Jan 2020 12:23:17 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 10 Jan 2020 12:23:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 376EB1063 for ; Fri, 10 Jan 2020 04:23:14 -0800 (PST) Received: from [10.2.80.62] (e120808-lin.cambridge.arm.com [10.2.80.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EAAD03F534 for ; Fri, 10 Jan 2020 04:23:13 -0800 (PST) To: "gcc-patches@gcc.gnu.org" From: Kyrill Tkachov Subject: [PATCH][wwwdocs] GCC 10 changes.html for arm and aarch64 Message-ID: <819bdd98-8a89-3426-f714-c19526b7db79@foss.arm.com> Date: Fri, 10 Jan 2020 12:23:11 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 Hi all, This patch adds initial entries for notable features that went in to GCC 10 on the arm and aarch64 front. The list is by no means complete so if you'd like your contribution called please shout or post a follow-up patch. It is, nevertheless, a decent start at the relevant sections in changes.html Thanks, Kyrill commit b539d38b322883ed5aa6563ac879af6a5ebabd96 Author: Kyrylo Tkachov Date: Thu Nov 7 17:58:45 2019 +0000 [arm/aarch64] GCC 10 changes.html diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html index d6108269..8f498017 100644 --- a/htdocs/gcc-10/changes.html +++ b/htdocs/gcc-10/changes.html @@ -322,17 +322,102 @@ a work-in-progress.

New Targets and Target Specific Improvements

- +

AArch64 & arm

+
    +
  • The AArch64 and arm ports now support condition flag output constraints + in inline assembly, as indicated by the __GCC_ASM_FLAG_OUTPUTS__. + On arm this feature is only available for A32 and T32 targets. + Please refer to the documentation for more details.
    • +
+ +

AArch64

+
    +
  • The -mbranch-protection=pac-ret option now accepts the + optional argument +b-key extension to perform return address + signing with the B-key instead of the A-key. +
    • +
  • The Transactional Memory Extension is now supported through ACLE + intrinsics. It can be enabled through the +tme option + extension (for example, -march=armv8.5-a+tme). +
    • +
  • Initial autovectorization support for SVE2 has been added and can be + enabled through the +sve2 option extension (for example, + -march=armv8.5-a+sve2). Additional extensions can be enabled + through +sve2-sm4, +sve2=aes, + +sve2-sha3, +sve2-bitperm. +
    • +
  • A number of features from the Armv8.5-a are now supported through ACLE + intrinsics. These include: +
      +
    • The random number instructions that can be enabled + through the (already present in GCC 9.1) +rng option + extension.
      • +
    • Floating-point intrinsics to round to integer instructions from + Armv8.5-a when targeting -march=armv8.5-a or later.
      • +
    • Memory Tagging Extension intrinsics enabled through the + +memtag option extension.
      • +
    +
    • +
  • The option -moutline-atomics has been added to aid + deployment of the Large System Extensions (LSE) on GNU/Linux systems built + with a baseline architecture targeting Armv8-A. When the option is + specified code is emitted to detect the presence of LSE instructions at + runtime and use them for standard atomic operations. + For more information please refer to the documentation. +
    • +
  • + Support has been added for the following processors + (GCC identifiers in parentheses): +
      +
    • Arm Cortex-A77 (cortex-a77).
      • +
    • Arm Cortex-A76AE (cortex-a76ae).
      • +
    • Arm Cortex-A65 (cortex-a65).
      • +
    • Arm Cortex-A65AE (cortex-a65ae).
      • +
    • Arm Cortex-A34 (cortex-a34).
      • +
    + The GCC identifiers can be used + as arguments to the -mcpu or -mtune options, + for example: -mcpu=cortex-a77 or + -mtune=cortex-a65ae or as arguments to the equivalent target + attributes and pragmas. +
    • +
-

ARM

+

arm

  • Support for the FDPIC ABI has been added. It uses 64-bit function descriptors to represent pointers to functions, and enables code sharing on MMU-less systems. The corresponding target triple is arm-uclinuxfdpiceabi, and the C library is uclibc-ng.
    • +
  • Support has been added for the Arm EABI on NetBSD through the + arm*-*-netbsdelf-*eabi* triplet. +
    • +
  • The handling of 64-bit integer operations has been significantly reworked + and improved leading to improved performance and reduced stack usage when using + 64-bit integral data types. The option -mneon-for-64bits is now + deprecated and will be removed in a future release.
    • +
  • + Support has been added for the following processors + (GCC identifiers in parentheses): +
      +
    • Arm Cortex-A77 (cortex-a77).
      • +
    • Arm Cortex-A76AE (cortex-a76ae).
      • +
    • Arm Cortex-M35P (cortex-m35p).
      • +
    + The GCC identifiers can be used + as arguments to the -mcpu or -mtune options, + for example: -mcpu=cortex-a77 or + -mtune=cortex-m35p. +
    • +
  • Support has been extended for the ACLE + + data-processing intrinsics to include 32-bit SIMD, saturating arithmetic, + 16-bit multiplication and other related intrinsics aimed at DSP algorithm + optimization. +