From patchwork Wed Jun 27 18:33:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 935667 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-480574-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="fg+SIVAd"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41GBP93bl9z9s2g for ; Thu, 28 Jun 2018 04:33:17 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=pSyU9zS1ZkWq7fPg8KRhPhki/M6weke9l2cPHBgTPi8Mp600qd mZcCO/D6VvqFg82wImcivOshh4rAlwfRA5g6KUHQAlwfP4CQ2qasi/7WVii96Ju+ RBL8HKHzkUaD2mHliQc+TMJT3tPgJC7WLmQC0wA2Gpxnp4mZbeMefWZko= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=Ru4Mfr4sEOBYvt4N5NfGurD/BD8=; b=fg+SIVAdDrM87TC46dDg 1FAPMykNLcpl7oQ5c56nz02Se0XMY2wnLuR3MTSBeXMnQfvh71rWDmdnwpN/YsdH YJ4NXECx3Y+aHgWUEwE3AT1JCT8HZK4OevA6iXhwGcmzHNqdE7kb2Kb3mvLVrwli kA/nNmjPgwPrmxHvxAJx/YU= Received: (qmail 73003 invoked by alias); 27 Jun 2018 18:33:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 72987 invoked by uid 89); 27 Jun 2018 18:33:09 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_HELO_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 27 Jun 2018 18:33:08 +0000 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 04A7130C10F4 for ; Wed, 27 Jun 2018 18:33:07 +0000 (UTC) Received: from localhost.localdomain (ovpn-112-5.rdu2.redhat.com [10.10.112.5]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7679D91F20 for ; Wed, 27 Jun 2018 18:33:04 +0000 (UTC) To: gcc-patches From: Jeff Law Subject: [committed] [3/3] Converting the v850 port away from cc0 -- add flag setting patterns Openpgp: preference=signencrypt Message-ID: <80945db7-9543-dc66-6ab3-768f2e8ef9fc@redhat.com> Date: Wed, 27 Jun 2018 12:33:03 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 X-IsSubscribed: yes This is strictly an optimization patch. It adds flag setting variants of key arithmetic, logical, extensions, shifts, etc. That in turn allows the compare-elim pass to do its job. At this point the v8 port is converted and should be functioning at the same level it was before the conversion. As I noted in the cover message, there are some further things that could be improved, the only one I plan to look at is conversion to LRA. Committed to the trunk. Jeff * config/v850/v850.md (addsi3_set_flags): New pattern. (subsi3_set_flags, negsi2_set_flags, andsi3_set_flags): Likewise. (iorsi3_set_flags, xorsi3_set_flags, one_cmplsi2_set_flags): Likewise. (zero_extendhisi2_v850_set_flags): Likewise. (zero_extendqisi2_v850_set_flags): Likewise. (ashlsi3_set_flags, ashlsi3_v850e2_set_flags): Likewise. (lshrsi3_set_flags, lshrsi3_v850e2_set_flags): Likewise. (ashrsi3_set_flags, ashrsi3_v850e2_set_flags): Likewise. diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md index 3cfec74..b8f098b 100644 --- a/gcc/config/v850/v850.md +++ b/gcc/config/v850/v850.md @@ -569,6 +569,20 @@ addi %O2(%P2),%1,%0" [(set_attr "length" "2,4,4")]) +(define_insn "addsi3_set_flags" + [(set (reg:CCNZ CC_REGNUM) + (compare:CCNZ (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r") + (match_operand:SI 2 "nonmemory_operand" "rJ,K,U")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r,r,r") + (plus:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + "@ + add %2,%0 + addi %2,%1,%0 + addi %O2(%P2),%1,%0" + [(set_attr "length" "2,4,4")]) + ;; ---------------------------------------------------------------------- ;; SUBTRACT INSTRUCTIONS ;; ---------------------------------------------------------------------- @@ -593,6 +607,19 @@ subr %1,%0" [(set_attr "length" "2,2")]) +(define_insn "*subsi3_set_flags" + [(set (reg:CCNZ CC_REGNUM) + (compare:CCNZ (minus:SI (match_operand:SI 1 "register_operand" "0,r") + (match_operand:SI 2 "nonmemory_operand" "r,0")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r,r") + (minus:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + "@ + sub %2,%0 + subr %1,%0" + [(set_attr "length" "2,2")]) + (define_insn_and_split "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "register_operand" "0")))] @@ -610,6 +637,16 @@ "subr %.,%0" [(set_attr "length" "2")]) +(define_insn "*negsi2_set_flags" + [(set (reg:CCNZ CC_REGNUM) + (compare:CCNZ (neg:SI (match_operand:SI 1 "register_operand" "0")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (match_dup 1)))] + "reload_completed" + "subr %.,%0" + [(set_attr "length" "2")]) + ;; ---------------------------------------------------------------------- ;; MULTIPLY INSTRUCTIONS ;; ---------------------------------------------------------------------- @@ -831,6 +868,20 @@ andi %2,%1,%0" [(set_attr "length" "2,2,4")]) +(define_insn "andsi3_set_flags" + [(set (reg:CC CC_REGNUM) + (compare:CC (and:SI (match_operand:SI 1 "register_operand" "%0,0,r") + (match_operand:SI 2 "nonmemory_operand" "r,I,M")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r,r,r") + (and:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + "@ + and %2,%0 + and %.,%0 + andi %2,%1,%0" + [(set_attr "length" "2,2,4")]) + ;; ---------------------------------------------------------------------- ;; OR INSTRUCTIONS ;; ---------------------------------------------------------------------- @@ -916,6 +967,20 @@ ori %2,%1,%0" [(set_attr "length" "2,2,4")]) +(define_insn "*iorsi3_set_flags" + [(set (reg:CC CC_REGNUM) + (compare:CC (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r") + (match_operand:SI 2 "nonmemory_operand" "r,I,M")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r,r,r") + (ior:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + "@ + or %2,%0 + or %.,%0 + ori %2,%1,%0" + [(set_attr "length" "2,2,4")]) + ;; ---------------------------------------------------------------------- ;; XOR INSTRUCTIONS ;; ---------------------------------------------------------------------- @@ -1001,6 +1066,20 @@ xori %2,%1,%0" [(set_attr "length" "2,2,4")]) +(define_insn "*xorsi3_set_flags" + [(set (reg:CC CC_REGNUM) + (compare:CC (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r") + (match_operand:SI 2 "nonmemory_operand" "r,I,M")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r,r,r") + (xor:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + "@ + xor %2,%0 + xor %.,%0 + xori %2,%1,%0" + [(set_attr "length" "2,2,4")]) + ;; ---------------------------------------------------------------------- ;; NOT INSTRUCTIONS @@ -1024,6 +1103,16 @@ "not %1,%0" [(set_attr "length" "2")]) +(define_insn "*one_cmplsi2_set_flags" + [(set (reg:CC CC_REGNUM) + (compare:CC (not:SI (match_operand:SI 1 "register_operand" "r")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (not:SI (match_dup 1)))] + "reload_completed" + "not %1,%0" + [(set_attr "length" "2")]) + ;; ----------------------------------------------------------------- ;; BIT FIELDS ;; ----------------------------------------------------------------- @@ -1808,6 +1897,16 @@ "andi 65535,%1,%0" [(set_attr "length" "4")]) +(define_insn "*zero_extendhisi2_v850_set_flags" + [(set (reg:CCNZ CC_REGNUM) + (compare:CCNZ (zero_extend:SI (match_operand:HI 1 "register_operand" "r")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (zero_extend:SI (match_dup 1)))] + "reload_completed" + "andi 65535,%1,%0" + [(set_attr "length" "4")]) + (define_expand "zero_extendhisi2" [(parallel [(set (match_operand:SI 0 "register_operand") (zero_extend:SI @@ -1841,6 +1940,16 @@ "andi 255,%1,%0" [(set_attr "length" "4")]) +(define_insn "*zero_extendqisi2_v850_set_flags" + [(set (reg:CCNZ CC_REGNUM) + (compare:CCNZ (zero_extend:SI (match_operand:QI 1 "register_operand" "r")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (zero_extend:SI (match_dup 1)))] + "reload_completed" + "andi 255,%1,%0" + [(set_attr "length" "4")]) + (define_expand "zero_extendqisi2" [(parallel [(set (match_operand:SI 0 "register_operand") (zero_extend:SI @@ -1941,6 +2050,19 @@ shl %2,%0" [(set_attr "length" "4,2")]) +(define_insn "ashlsi3_set_flags" + [(set (reg:CCNZ CC_REGNUM) + (compare:CCNZ (ashift:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "r,N")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r,r") + (ashift:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + "@ + shl %2,%0 + shl %2,%0" + [(set_attr "length" "4,2")]) + (define_insn "ashlsi3_v850e2_clobber_flags" [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI @@ -1951,6 +2073,17 @@ "shl %2,%1,%0" [(set_attr "length" "4")]) +(define_insn "ashlsi3_v850e2_set_flags" + [(set (reg:CCNZ CC_REGNUM) + (compare:CCNZ (ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "nonmemory_operand" "r")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI (match_dup 1) (match_dup 2)))] + "reload_completed && TARGET_V850E2_UP" + "shl %2,%1,%0" + [(set_attr "length" "4")]) + (define_insn_and_split "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") (lshiftrt:SI @@ -1974,6 +2107,19 @@ shr %2,%0" [(set_attr "length" "4,2")]) +(define_insn "lshrsi3_set_flags" + [(set (reg:CC CC_REGNUM) + (compare:CC (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "r,N")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r,r") + (lshiftrt:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + "@ + shr %2,%0 + shr %2,%0" + [(set_attr "length" "4,2")]) + (define_insn "lshrsi3_v850e2_clobber_flags" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI @@ -1984,6 +2130,17 @@ "shr %2,%1,%0" [(set_attr "length" "4")]) +(define_insn "lshrsi3_v850e2_set_flags" + [(set (reg:CC CC_REGNUM) + (compare:CC (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "nonmemory_operand" "r")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (lshiftrt:SI (match_dup 1) (match_dup 2)))] + "reload_completed && TARGET_V850E2_UP" + "shr %2,%1,%0" + [(set_attr "length" "4")]) + (define_insn_and_split "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") (ashiftrt:SI @@ -2007,6 +2164,19 @@ sar %2,%0" [(set_attr "length" "4,2")]) +(define_insn "ashrsi3_set_flags" + [(set (reg:CC CC_REGNUM) + (compare:CC (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "r,N")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r,r") + (ashiftrt:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + "@ + sar %2,%0 + sar %2,%0" + [(set_attr "length" "4,2")]) + (define_insn "ashrsi3_v850e2_clobber_flags" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI @@ -2017,6 +2187,17 @@ "sar %2,%1,%0" [(set_attr "length" "4")]) +(define_insn "ashrsi3_v850e2_set_flags" + [(set (reg:CC CC_REGNUM) + (compare:CC (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "nonmemory_operand" "r")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (ashiftrt:SI (match_dup 1) (match_dup 2)))] + "reload_completed && TARGET_V850E2_UP" + "sar %2,%1,%0" + [(set_attr "length" "4")]) + ;; ---------------------------------------------------------------------- ;; FIND FIRST BIT INSTRUCTION ;; ----------------------------------------------------------------------