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[X86_64] : fix operand constraints in sse3_mwait

Message ID 7794A52CE4D579448B959EED7DD0A4723DD0D668@satlexdag06.amd.com
State New
Headers show

Commit Message

Kumar, Venkataramanan June 4, 2015, 3:13 p.m. UTC 
Hi Uros, 

As discussed here https://gcc.gnu.org/ml/gcc/2015-06/msg00043.html

I am going to install the following patch to trunk.

GCC bootstrap and regressions tests passed.

Regards,
Venkat.
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Patch

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ab5c004..2fa6e96 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@ 
+2015-06-04  Venkataramanan Kumar  <Venkataramanan.kumar>
+
+       * config/i386/sse.md (sse3_mwait): Swap the operand constraints.
+
 2015-06-02  Alan Modra  <amodra@gmail.com>

        * config/rs6000/vsx.md (vsx_extract_v4sf): Revert accidental
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 21c6c6c..2685f06 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13194,10 +13194,12 @@ 
    (set_attr "atom_sse_attr" "fence")
    (set_attr "memory" "unknown")])

-
+;; As per AMD and Intel ISA manuals, the first operand is extensions
+;; and it goes to %ecx. The second operand received is hints and it goes
+;; to %eax.
 (define_insn "sse3_mwait"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
-                    (match_operand:SI 1 "register_operand" "c")]
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")
+                    (match_operand:SI 1 "register_operand" "a")]
                    UNSPECV_MWAIT)]
   "TARGET_SSE3"
 ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.