diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b03c6c1..13fbb7eb 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4633,9 +4633,10 @@ (define_split
 
 
 (define_expand "ashr<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
-	(ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
-		      (match_operand:SI 2 "reg_or_cint_operand" "")))]
+  [(parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
+		   (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+				 (match_operand:SI 2 "reg_or_cint_operand" "")))
+	      (clobber (reg:GPR CA_REGNO))])]
   ""
 {
   /* The generic code does not generate optimal code for the low word
@@ -4657,7 +4658,8 @@ (define_expand "ashr<mode>3"
 (define_insn "*ashr<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-		      (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
+		      (match_operand:SI 2 "reg_or_cint_operand" "rn")))
+   (clobber (reg:GPR CA_REGNO))]
   ""
   "sra<wd>%I2 %0,%1,%<hH>2"
   [(set_attr "type" "shift")
@@ -4667,7 +4669,8 @@ (define_insn "*ashrsi3_64"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(sign_extend:DI
 	    (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
+			 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))
+   (clobber (reg:SI CA_REGNO))]
   "TARGET_POWERPC64"
   "sraw%I2 %0,%1,%h2"
   [(set_attr "type" "shift")
@@ -4678,15 +4681,17 @@ (define_insn_and_split "*ashr<mode>3_dot"
 	(compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
 				  (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
 		    (const_int 0)))
-   (clobber (match_scratch:GPR 0 "=r,r"))]
+   (clobber (match_scratch:GPR 0 "=r,r"))
+   (clobber (reg:GPR CA_REGNO))]
   "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
    sra<wd>%I2. %0,%1,%<hH>2
    #"
   "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-	(ashiftrt:GPR (match_dup 1)
-		      (match_dup 2)))
+  [(parallel [(set (match_dup 0)
+		   (ashiftrt:GPR (match_dup 1)
+				 (match_dup 2)))
+	      (clobber (reg:GPR CA_REGNO))])
    (set (match_dup 3)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
@@ -4703,15 +4708,17 @@ (define_insn_and_split "*ashr<mode>3_dot2"
 		    (const_int 0)))
    (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
 	(ashiftrt:GPR (match_dup 1)
-		      (match_dup 2)))]
+		      (match_dup 2)))
+   (clobber (reg:GPR CA_REGNO))]
   "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
    sra<wd>%I2. %0,%1,%<hH>2
    #"
   "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-	(ashiftrt:GPR (match_dup 1)
-		      (match_dup 2)))
+  [(parallel [(set (match_dup 0)
+		   (ashiftrt:GPR (match_dup 1)
+				 (match_dup 2)))
+	      (clobber (reg:GPR CA_REGNO))])
    (set (match_dup 3)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
@@ -6152,8 +6159,9 @@ (define_insn_and_split "floatdisf2_internal1"
 ;; by a bit that won't be lost at that stage, but is below the SFmode
 ;; rounding position.
 (define_expand "floatdisf2_internal2"
-  [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
-				   (const_int 53)))
+  [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
+					      (const_int 53)))
+	      (clobber (reg:DI CA_REGNO))])
    (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
 					   (const_int 2047)))
    (set (match_dup 3) (plus:DI (match_dup 3)
@@ -6316,9 +6324,9 @@ (define_insn "*negdi2_noppc64"
 (define_insn "ashrdi3_no_power"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
 	(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		     (match_operand:SI 2 "const_int_operand" "M,i")))]
+		     (match_operand:SI 2 "const_int_operand" "M,i")))
+   (clobber (reg:SI CA_REGNO))]
   "!TARGET_POWERPC64"
-  "*
 {
   switch (which_alternative)
     {
@@ -6335,7 +6343,7 @@ (define_insn "ashrdi3_no_power"
       else
 	return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
     }
-}"
+}
   [(set_attr "type" "two,three")
    (set_attr "length" "8,12")])
 
