From patchwork Fri May 26 14:19:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 767407 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wZ7Z442JRz9s7r for ; Sat, 27 May 2017 00:19:55 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="OWsHXq9M"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=IqtSR+3crPINkWoCikd8acJANPSoVpWBwQ1H1cNyFddJRHrX6D bSsQA5r16pGKeV7bwPRUQpE5TeZG//htwfZ9xju/cLDqY05ZwhtJCkhbqtaOJPI1 /uQiRDbwCkEhxzXWj5VkBwnGebOfLyDZRmVLAhdcjtpLw8A1EVJz0WsLM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=UsBcQc3kA5rKYleerUs6tWp7Xcw=; b=OWsHXq9MdH+Ivgfst2TQ S0DGt7ZenjqAggob4ygvHxFcfWtziAfGhu2oJH68vudsfWnOO0pTByihqgAnieFS WWrtcFabFsJv9KCc7juL7ouaGMtw2wwiDKFrRAgZvATBXjcp/gtYLpLig7f7nc+d pfyje0X3jns6Oo6QG+gcRy8= Received: (qmail 77634 invoked by alias); 26 May 2017 14:19:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 77588 invoked by uid 89); 26 May 2017 14:19:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=H*M:98e8, H*MI:98e8, HX-Envelope-From:sk:thomas. X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 26 May 2017 14:19:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2351C1596; Fri, 26 May 2017 07:19:43 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 42B6E3F578; Fri, 26 May 2017 07:19:42 -0700 (PDT) To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" From: Thomas Preudhomme Subject: [PATCH, GCC/ARM] Rename *_compute_save_reg_mask () Message-ID: <74536026-0417-4dd2-98e8-a21e92699f2a@foss.arm.com> Date: Fri, 26 May 2017 15:19:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 X-IsSubscribed: yes Hi, Name of arm_compute_save_reg_mask and thumb1_compute_save_reg_mask suggest that all register saving computation is done in these function but these only deal with core registers. The caller arm_compute_frame_layout () also computes some of the register saving, eg. for VFP registers in 32bit targets. This commit rename former functions to refer to core registers saving. ChangeLog entry is as follows: *** gcc/ChangeLog *** 2017-05-24 Thomas Preud'homme * config/arm/arm.c (arm_compute_save_reg_mask): Rename into ... (arm_compute_save_core_reg_mask): This. (thumb1_compute_save_reg_mask): Rename into ... (thumb1_compute_save_core_reg_mask): This. (arm_compute_save_reg0_reg12_mask): Adapt comment. (arm_compute_frame_layout): Likewise. Ok for trunk? Tested with a successful arm-none-eabi build. Best regards, Thomas diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c6036fe24abe761540374cfed36edcb953703f5b..6a4ab358d5ee5ceef6a3a1cdfa630dece25cd143 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -130,7 +130,7 @@ static void push_minipool_fix (rtx_insn *, HOST_WIDE_INT, rtx *, static void arm_reorg (void); static void note_invalid_constants (rtx_insn *, HOST_WIDE_INT, int); static unsigned long arm_compute_save_reg0_reg12_mask (void); -static unsigned long arm_compute_save_reg_mask (void); +static unsigned long arm_compute_save_core_reg_mask (void); static unsigned long arm_isr_value (tree); static unsigned long arm_compute_func_type (void); static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); @@ -19030,7 +19030,7 @@ output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) && reg >= FIRST_HI_REGNUM && reg <= LAST_HI_REGNUM)) /* Compute the register save mask for registers 0 through 12 - inclusive. This code is used by arm_compute_save_reg_mask. */ + inclusive. This code is used by arm_compute_save_core_reg_mask (). */ static unsigned long arm_compute_save_reg0_reg12_mask (void) @@ -19157,12 +19157,12 @@ arm_compute_static_chain_stack_bytes (void) return 0; } -/* Compute a bit mask of which registers need to be +/* Compute a bit mask of which core registers need to be saved on the stack for the current function. This is used by arm_compute_frame_layout, which may add extra registers. */ static unsigned long -arm_compute_save_reg_mask (void) +arm_compute_save_core_reg_mask (void) { unsigned int save_reg_mask = 0; unsigned long func_type = arm_current_func_type (); @@ -19244,10 +19244,10 @@ arm_compute_save_reg_mask (void) return save_reg_mask; } -/* Compute a bit mask of which registers need to be +/* Compute a bit mask of which core registers need to be saved on the stack for the current function. */ static unsigned long -thumb1_compute_save_reg_mask (void) +thumb1_compute_save_core_reg_mask (void) { unsigned long mask; unsigned reg; @@ -20783,7 +20783,7 @@ any_sibcall_could_use_r3 (void) eliminating some of the registers. The values returned by this function must reflect the behavior - of arm_expand_prologue() and arm_compute_save_reg_mask(). + of arm_expand_prologue () and arm_compute_save_core_reg_mask (). The sign of the number returned reflects the direction of stack growth, so the values are positive for all eliminations except @@ -20839,7 +20839,7 @@ arm_compute_frame_layout (void) { unsigned int regno; - offsets->saved_regs_mask = arm_compute_save_reg_mask (); + offsets->saved_regs_mask = arm_compute_save_core_reg_mask (); core_saved = bit_count (offsets->saved_regs_mask) * 4; saved = core_saved; @@ -20870,7 +20870,7 @@ arm_compute_frame_layout (void) } else /* TARGET_THUMB1 */ { - offsets->saved_regs_mask = thumb1_compute_save_reg_mask (); + offsets->saved_regs_mask = thumb1_compute_save_core_reg_mask (); core_saved = bit_count (offsets->saved_regs_mask) * 4; saved = core_saved; if (TARGET_BACKTRACE)