From patchwork Tue Feb 7 12:02:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prachi Godbole X-Patchwork-Id: 725088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vHjfD2TS2z9s7c for ; Tue, 7 Feb 2017 23:03:15 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ESk8xu/B"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=Ijl /Qm/FtyjzDzFGF5qarlrLsR+JTjjVrRtmfwowD6icfkyxrUSRtVZHTNzEqZw/7S2 qCobjn1Ll7U3FylyqGqVZJ/KPO02acA0BcKYOsiM32AX8PeiH9A2gyHdblrtXQGk Exi1iFoRVREzro5tnut6NyPU1lGQzH49pI2xSeJA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=VLTl51AHt uSEAyzux61e71HnkCI=; b=ESk8xu/BDkLtNk3KqXB64/v2ipQ7sJ202iRqE/4FI VHjTBRr5duRPV5ZwgtagT1WBDmQktfib+VrZbpIH9BphoV/pKBVeMhD7OmxC7gjx FOnJUnpzzKPO4DSlAtwo5pF+Ewz7XwGOkl7f7gGwfojnRqBi+g47Im/9e7YjDoW7 Jk= Received: (qmail 3253 invoked by alias); 7 Feb 2017 12:03:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 3239 invoked by uid 89); 7 Feb 2017 12:03:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=BAYES_00, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, SPF_PASS autolearn=no version=3.3.2 spammy=rtvec, rtvec_alloc, doubleword, VAL X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 07 Feb 2017 12:02:56 +0000 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 52F306E5D3B8 for ; Tue, 7 Feb 2017 12:02:50 +0000 (GMT) Received: from PUMAIL01.pu.imgtec.org (192.168.91.250) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 7 Feb 2017 12:02:52 +0000 Received: from PUMAIL01.pu.imgtec.org ([::1]) by PUMAIL01.pu.imgtec.org ([::1]) with mapi id 14.03.0266.001; Tue, 7 Feb 2017 17:32:46 +0530 From: Prachi Godbole To: "gcc-patches@gcc.gnu.org" CC: Matthew Fortune Subject: [PATCH][MIPS] MSA machine description fixes Date: Tue, 7 Feb 2017 12:02:46 +0000 Message-ID: <72E73D4BBFC6704695754C43662FC584C4F54EBE@PUMAIL01.pu.imgtec.org> MIME-Version: 1.0 Hi, The patch fixes some bugs as mentioned below. 1. mips_gen_const_int_vector(): Change type for argument VAL from int to HOST_WIDE_INT to allow const vector of type doubleword. It in turn enables generation of BCLRI.d instead of AND.d for immediate const vector operand with only one bit clear. 2. MSA dot product family instruction for .d format: Fix wrong MODE for vec_select in the second mult operand. It enables some optimizations like CSE fwprop etc. 3. signed min/max immediate: Fix print operand code so as to print signed immediate instead of an unsigned one. 4. MSA max/min absolute instruction family: Introduce mode iterator in if_then_else construct. It enables some optimizations like CSE fwprop etc. Tests for all of them are also included in the patch. Ok for trunk? Regards, Prachi Changelog: 2017-02-07 Prachi Godbole gcc/ * config/mips/mips-msa.md (msa_dotp__d, msa_dpadd__d, msa_dpsub__d): Fix MODE for vec_select. (msa_fmax_a_, msa_fmin_a_, msa_max_a_, msa_min_a_): Introduce mode interator for if_then_else. (smin3, smax3): Change operand print code from 'B' to 'E'. * config/mips/mips.c (mips_gen_const_int_vector): Change type of last argument. * config/mips/mips-protos.h (mips_gen_const_int_vector): Likewise. gcc/testsuite/ * gcc.target/mips/msa-1.c: New tests. Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c (revision 245205) +++ gcc/config/mips/mips.c (working copy) @@ -21608,7 +21608,7 @@ /* Return a const_int vector of VAL with mode MODE. */ rtx -mips_gen_const_int_vector (machine_mode mode, int val) +mips_gen_const_int_vector (machine_mode mode, HOST_WIDE_INT val) { int nunits = GET_MODE_NUNITS (mode); rtvec v = rtvec_alloc (nunits); Index: gcc/config/mips/mips-protos.h =================================================================== --- gcc/config/mips/mips-protos.h (revision 245205) +++ gcc/config/mips/mips-protos.h (working copy) @@ -294,7 +294,7 @@ extern bool mips_const_vector_bitimm_set_p (rtx, machine_mode); extern bool mips_const_vector_bitimm_clr_p (rtx, machine_mode); extern rtx mips_msa_vec_parallel_const_half (machine_mode, bool); -extern rtx mips_gen_const_int_vector (machine_mode, int); +extern rtx mips_gen_const_int_vector (machine_mode, HOST_WIDE_INT); extern bool mips_secondary_memory_needed (enum reg_class, enum reg_class, machine_mode); extern bool mips_cannot_change_mode_class (machine_mode, Index: gcc/config/mips/mips-msa.md =================================================================== --- gcc/config/mips/mips-msa.md (revision 245205) +++ gcc/config/mips/mips-msa.md (working copy) @@ -1230,10 +1230,10 @@ (parallel [(const_int 0) (const_int 2)])))) (mult:V2DI (any_extend:V2DI - (vec_select:V4SI (match_dup 1) + (vec_select:V2SI (match_dup 1) (parallel [(const_int 1) (const_int 3)]))) (any_extend:V2DI - (vec_select:V4SI (match_dup 2) + (vec_select:V2SI (match_dup 2) (parallel [(const_int 1) (const_int 3)]))))))] "ISA_HAS_MSA" "dotp_.d\t%w0,%w1,%w2" @@ -1319,10 +1319,10 @@ (parallel [(const_int 0) (const_int 2)])))) (mult:V2DI (any_extend:V2DI - (vec_select:V4SI (match_dup 2) + (vec_select:V2SI (match_dup 2) (parallel [(const_int 1) (const_int 3)]))) (any_extend:V2DI - (vec_select:V4SI (match_dup 3) + (vec_select:V2SI (match_dup 3) (parallel [(const_int 1) (const_int 3)]))))) (match_operand:V2DI 1 "register_operand" "0")))] "ISA_HAS_MSA" @@ -1414,10 +1414,10 @@ (parallel [(const_int 0) (const_int 2)])))) (mult:V2DI (any_extend:V2DI - (vec_select:V4SI (match_dup 2) + (vec_select:V2SI (match_dup 2) (parallel [(const_int 1) (const_int 3)]))) (any_extend:V2DI - (vec_select:V4SI (match_dup 3) + (vec_select:V2SI (match_dup 3) (parallel [(const_int 1) (const_int 3)])))))))] "ISA_HAS_MSA" "dpsub_.d\t%w0,%w2,%w3" @@ -1688,7 +1688,7 @@ (define_insn "msa_fmax_a_" [(set (match_operand:FMSA 0 "register_operand" "=f") - (if_then_else + (if_then_else:FMSA (gt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f")) (abs:FMSA (match_operand:FMSA 2 "register_operand" "f"))) (match_dup 1) @@ -1709,7 +1709,7 @@ (define_insn "msa_fmin_a_" [(set (match_operand:FMSA 0 "register_operand" "=f") - (if_then_else + (if_then_else:FMSA (lt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f")) (abs:FMSA (match_operand:FMSA 2 "register_operand" "f"))) (match_dup 1) @@ -2174,7 +2174,7 @@ (define_insn "msa_max_a_" [(set (match_operand:IMSA 0 "register_operand" "=f") - (if_then_else + (if_then_else:IMSA (gt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")) (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))) (match_dup 1) @@ -2191,7 +2191,7 @@ "ISA_HAS_MSA" "@ max_s.\t%w0,%w1,%w2 - maxi_s.\t%w0,%w1,%B2" + maxi_s.\t%w0,%w1,%E2" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) @@ -2208,7 +2208,7 @@ (define_insn "msa_min_a_" [(set (match_operand:IMSA 0 "register_operand" "=f") - (if_then_else + (if_then_else:IMSA (lt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")) (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))) (match_dup 1) @@ -2225,7 +2225,7 @@ "ISA_HAS_MSA" "@ min_s.\t%w0,%w1,%w2 - mini_s.\t%w0,%w1,%B2" + mini_s.\t%w0,%w1,%E2" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) Index: gcc/testsuite/gcc.target/mips/msa-1.c =================================================================== --- gcc/testsuite/gcc.target/mips/msa-1.c (revision 0) +++ gcc/testsuite/gcc.target/mips/msa-1.c (revision 0) @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */ + +typedef int v4i32 __attribute__ ((vector_size(16))); +typedef long long v2i64 __attribute__ ((vector_size(16))); +typedef float v4f32 __attribute__ ((vector_size(16))); + +/* Test MSA AND.d optimization: generate BCLRI.d instead, for immediate const + vector operand with only one bit clear. */ + +void +and_d_msa (v2i64 *vx, v2i64 *vy) +{ + v2i64 and_vec = {0x7FFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFFF}; + *vy = (*vx) & and_vec; +} + +/* Test MSA dot product family for CSE optimization. */ + +static v4i32 g = {0, 92, 93, 94}; +static v4i32 h = {12, 24, 36, 48}; +static v2i64 l = {84, 98}; + +void +dotp_d_msa (v2i64 *c) +{ + l = __builtin_msa_dotp_s_d (g, h); +} + +void +dpadd_d_msa (v2i64 *c) +{ + *c = __builtin_msa_dpadd_s_d (l, g, h); +} + +void +dpsub_d_msa (v2i64 *c) +{ + *c = __builtin_msa_dpsub_s_d (l, g, h); +} + +/* Test MSA signed min/max immediate for correct assembly output. */ + +void +min_s_msa (v4i32 *vx, v4i32 *vy) +{ + *vy = __builtin_msa_mini_s_w (*vx, -15); +} +/* { dg-final { scan-assembler "-15" } } */ + +void +max_s_msa (v4i32 *vx, v4i32 *vy) +{ + *vy = __builtin_msa_maxi_s_w (*vx, -15); +} +/* { dg-final { scan-assembler "-15" } } */ + +/* Test MSA min_a/max_a instructions for forward propagation optimization. */ + +#define FUNC(NAME, TYPE, RETTYPE) RETTYPE NAME##_a_msa (TYPE *vx, TYPE *vy) \ +{ \ + TYPE dest = __builtin_msa_##NAME##_a_w (*vx, *vy); \ + return dest[0]; \ +} + +FUNC(fmin, v4f32, float) +FUNC(fmax, v4f32, float) +FUNC(min, v4i32, int) +FUNC(max, v4i32, int)