From patchwork Tue Nov 8 13:36:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 692305 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tCr1n1f8nz9t0w for ; Wed, 9 Nov 2016 00:36:29 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="fVtREa85"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=NrBvg8HrJJgnBdNRV GcHVYNKcpN9LoQ3oeVL3T+b0Hy6akA7o/tGdYIGq4RK7GZbU2RJMNcVxR/k3y3J9 qn+UeJE1ME3BR7PLIN8Jvw5UwUpc9fAlV0dUVjaXWli3E04wgvf+XMsfhXLIONRM awnSSRxnHPliFVQizzejdCOVLY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=Y1TsBVBFAtSdIb16MFtCkAl nj14=; b=fVtREa858uy4OgxcfTd0e0d/fiyA5XxtlZSKqnnxSayhUGq4oGipo32 xhhDtzeWp309hYufxJ502bFevxKZJGrDUiNTLhw5TEaQC8QroAb/4hrrhJeRfTjm sOPpPK6Y/u9ILk095dvfpuFmg/SULsRG2M4Lz6raKLNfrkwlab6M= Received: (qmail 99798 invoked by alias); 8 Nov 2016 13:36:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 99787 invoked by uid 89); 8 Nov 2016 13:36:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=BAYES_05, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=terry, Terry, manipulated, wireless X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 08 Nov 2016 13:36:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7BFC5CF6; Tue, 8 Nov 2016 05:36:08 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B89F23F25D; Tue, 8 Nov 2016 05:36:07 -0800 (PST) Subject: Re: [PATCH, GCC/ARM, ping] Optional -mthumb for Thumb only targets To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: From: Thomas Preudhomme Message-ID: <6daf8127-be12-2080-82d0-f6f9c00eca5a@foss.arm.com> Date: Tue, 8 Nov 2016 13:36:06 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: X-IsSubscribed: yes Ping? Best regards, Thomas On 25/10/16 18:07, Thomas Preudhomme wrote: > Hi, > > Currently when a user compiles for a thumb-only target (such as Cortex-M > processors) without specifying the -mthumb option GCC throws the error "target > CPU does not support ARM mode". This is suboptimal from a usability point of > view: the -mthumb could be deduced from the -march or -mcpu option when there is > no ambiguity. > > This patch implements this behavior by extending the DRIVER_SELF_SPECS to > automatically append -mthumb to the command line for thumb-only targets. It does > so by checking the last -march option if any is given or the last -mcpu option > otherwise. There is no ordering issue because conflicting -mcpu and -march is > already handled. > > Note that the logic cannot be implemented in function arm_option_override > because we need to provide the modified command line to the GCC driver for > finding the right multilib path and the function arm_option_override is executed > too late for that effect. > > ChangeLog entries are as follow: > > *** gcc/ChangeLog *** > > 2016-10-18 Terry Guo > Thomas Preud'homme > > PR target/64802 > * common/config/arm/arm-common.c (arm_target_thumb_only): New function. > * config/arm/arm-opts.h: Include arm-flags.h. > (struct arm_arch_core_flag): Define. > (arm_arch_core_flags): Define. > * config/arm/arm-protos.h: Include arm-flags.h. > (FL_NONE, FL_ANY, FL_CO_PROC, FL_ARCH3M, FL_MODE26, FL_MODE32, > FL_ARCH4, FL_ARCH5, FL_THUMB, FL_LDSCHED, FL_STRONG, FL_ARCH5E, > FL_XSCALE, FL_ARCH6, FL_VFPV2, FL_WBUF, FL_ARCH6K, FL_THUMB2, FL_NOTM, > FL_THUMB_DIV, FL_VFPV3, FL_NEON, FL_ARCH7EM, FL_ARCH7, FL_ARM_DIV, > FL_ARCH8, FL_CRC32, FL_SMALLMUL, FL_NO_VOLATILE_CE, FL_IWMMXT, > FL_IWMMXT2, FL_ARCH6KZ, FL2_ARCH8_1, FL2_ARCH8_2, FL2_FP16INST, > FL_TUNE, FL_FOR_ARCH2, FL_FOR_ARCH3, FL_FOR_ARCH3M, FL_FOR_ARCH4, > FL_FOR_ARCH4T, FL_FOR_ARCH5, FL_FOR_ARCH5T, FL_FOR_ARCH5E, > FL_FOR_ARCH5TE, FL_FOR_ARCH5TEJ, FL_FOR_ARCH6, FL_FOR_ARCH6J, > FL_FOR_ARCH6K, FL_FOR_ARCH6Z, FL_FOR_ARCH6ZK, FL_FOR_ARCH6KZ, > FL_FOR_ARCH6T2, FL_FOR_ARCH6M, FL_FOR_ARCH7, FL_FOR_ARCH7A, > FL_FOR_ARCH7VE, FL_FOR_ARCH7R, FL_FOR_ARCH7M, FL_FOR_ARCH7EM, > FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A, FL2_FOR_ARCH8_2A, FL_FOR_ARCH8M_BASE, > FL_FOR_ARCH8M_MAIN, arm_feature_set, ARM_FSET_MAKE, > ARM_FSET_MAKE_CPU1, ARM_FSET_MAKE_CPU2, ARM_FSET_CPU1, ARM_FSET_CPU2, > ARM_FSET_EMPTY, ARM_FSET_ANY, ARM_FSET_HAS_CPU1, ARM_FSET_HAS_CPU2, > ARM_FSET_HAS_CPU, ARM_FSET_ADD_CPU1, ARM_FSET_ADD_CPU2, > ARM_FSET_DEL_CPU1, ARM_FSET_DEL_CPU2, ARM_FSET_UNION, ARM_FSET_INTER, > ARM_FSET_XOR, ARM_FSET_EXCLUDE, ARM_FSET_IS_EMPTY, > ARM_FSET_CPU_SUBSET): Move to ... > * config/arm/arm-flags.h: This new file. > * config/arm/arm.h (TARGET_MODE_SPEC_FUNCTIONS): Define. > (EXTRA_SPEC_FUNCTIONS): Add TARGET_MODE_SPEC_FUNCTIONS to its value. > (TARGET_MODE_SPECS): Define. > (DRIVER_SELF_SPECS): Add TARGET_MODE_SPECS to its value. > > > *** gcc/testsuite/ChangeLog *** > > 2016-10-11 Thomas Preud'homme > > PR target/64802 > * gcc.target/arm/optional_thumb-1.c: New test. > * gcc.target/arm/optional_thumb-2.c: New test. > * gcc.target/arm/optional_thumb-3.c: New test. > > > No regression when running the testsuite for -mcpu=cortex-m0 -mthumb, > -mcpu=cortex-m0 -marm and -mcpu=cortex-a8 -marm > > Is this ok for trunk? > > Best regards, > > Thomas diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index a9abd6b026e2f35844e810fecf09e9890ea41e21..29ae0c35dd036a5293a51dc16f356e6ed668d3c2 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -97,6 +97,29 @@ arm_rewrite_mcpu (int argc, const char **argv) return arm_rewrite_selected_cpu (argv[argc - 1]); } +/* Called by the driver to check whether the target denoted by current + command line options is a Thumb-only target. ARGV is an array of + -march and -mcpu values (ie. it contains the rhs after the equal + sign) and we use the last one of them to make a decision. The + number of elements in ARGV is given in ARGC. */ +const char * +arm_target_thumb_only (int argc, const char **argv) +{ + unsigned int opt; + + if (argc) + { + for (opt = 0; opt < (ARRAY_SIZE (arm_arch_core_flags)); opt++) + if ((strcmp (argv[argc - 1], arm_arch_core_flags[opt].name) == 0) + && !ARM_FSET_HAS_CPU1(arm_arch_core_flags[opt].flags, FL_NOTM)) + return "-mthumb"; + + return NULL; + } + else + return NULL; +} + #undef ARM_CPU_NAME_LENGTH diff --git a/gcc/config/arm/arm-flags.h b/gcc/config/arm/arm-flags.h new file mode 100644 index 0000000000000000000000000000000000000000..9a5991aa07a229a7741e526c2876e7e0e4749db4 --- /dev/null +++ b/gcc/config/arm/arm-flags.h @@ -0,0 +1,210 @@ +/* Flags used to identify the presence of processor capabilities. + + Copyright (C) 2016 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#ifndef GCC_ARM_FLAGS_H +#define GCC_ARM_FLAGS_H + +/* Flags used to identify the presence of processor capabilities. */ + +/* Bit values used to identify processor capabilities. */ +#define FL_NONE (0) /* No flags. */ +#define FL_ANY (0xffffffff) /* All flags. */ +#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ +#define FL_ARCH3M (1 << 1) /* Extended multiply */ +#define FL_MODE26 (1 << 2) /* 26-bit mode support */ +#define FL_MODE32 (1 << 3) /* 32-bit mode support */ +#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ +#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ +#define FL_THUMB (1 << 6) /* Thumb aware */ +#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ +#define FL_STRONG (1 << 8) /* StrongARM */ +#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ +#define FL_XSCALE (1 << 10) /* XScale */ +/* spare (1 << 11) */ +#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds + media instructions. */ +#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ +#define FL_WBUF (1 << 14) /* Schedule for write buffer ops. + Note: ARM6 & 7 derivatives only. */ +#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ +#define FL_THUMB2 (1 << 16) /* Thumb-2. */ +#define FL_NOTM (1 << 17) /* Instructions not present in the 'M' + profile. */ +#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */ +#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ +#define FL_NEON (1 << 20) /* Neon instructions. */ +#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M + architecture. */ +#define FL_ARCH7 (1 << 22) /* Architecture 7. */ +#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */ +#define FL_ARCH8 (1 << 24) /* Architecture 8. */ +#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */ + +#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */ +#define FL_NO_VOLATILE_CE (1 << 27) /* No volatile memory in IT block. */ + +#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ +#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ +#define FL_ARCH6KZ (1 << 31) /* ARMv6KZ architecture. */ + +#define FL2_ARCH8_1 (1 << 0) /* Architecture 8.1. */ +#define FL2_ARCH8_2 (1 << 1) /* Architecture 8.2. */ +#define FL2_FP16INST (1 << 2) /* FP16 Instructions for ARMv8.2 and + later. */ + +/* Flags that only effect tuning, not available instructions. */ +#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ + | FL_CO_PROC) + +#define FL_FOR_ARCH2 FL_NOTM +#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) +#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) +#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) +#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) +#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) +#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) +#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) +#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) +#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE +#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) +#define FL_FOR_ARCH6J FL_FOR_ARCH6 +#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) +#define FL_FOR_ARCH6Z FL_FOR_ARCH6 +#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K +#define FL_FOR_ARCH6KZ (FL_FOR_ARCH6K | FL_ARCH6KZ) +#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) +#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) +#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) +#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) +#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV) +#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV) +#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV) +#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) +#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8) +#define FL2_FOR_ARCH8_1A FL2_ARCH8_1 +#define FL2_FOR_ARCH8_2A (FL2_FOR_ARCH8_1A | FL2_ARCH8_2) +#define FL_FOR_ARCH8M_BASE (FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV) +#define FL_FOR_ARCH8M_MAIN (FL_FOR_ARCH7M | FL_ARCH8) + +/* There are too many feature bits to fit in a single word so the set of cpu and + fpu capabilities is a structure. A feature set is created and manipulated + with the ARM_FSET macros. */ + +typedef struct +{ + unsigned long cpu[2]; +} arm_feature_set; + + +/* Initialize a feature set. */ + +#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } } + +#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE)) +#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2)) + +/* Accessors. */ + +#define ARM_FSET_CPU1(S) ((S).cpu[0]) +#define ARM_FSET_CPU2(S) ((S).cpu[1]) + +/* Useful combinations. */ + +#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE) +#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY) + +/* Tests for a specific CPU feature. */ + +#define ARM_FSET_HAS_CPU1(A, F) \ + (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F))) +#define ARM_FSET_HAS_CPU2(A, F) \ + (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F))) +#define ARM_FSET_HAS_CPU(A, F1, F2) \ + (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2))) + +/* Add a feature to a feature set. */ + +#define ARM_FSET_ADD_CPU1(DST, F) \ + do { \ + (DST).cpu[0] |= (F); \ + } while (0) + +#define ARM_FSET_ADD_CPU2(DST, F) \ + do { \ + (DST).cpu[1] |= (F); \ + } while (0) + +/* Remove a feature from a feature set. */ + +#define ARM_FSET_DEL_CPU1(DST, F) \ + do { \ + (DST).cpu[0] &= ~(F); \ + } while (0) + +#define ARM_FSET_DEL_CPU2(DST, F) \ + do { \ + (DST).cpu[1] &= ~(F); \ + } while (0) + +/* Union of feature sets. */ + +#define ARM_FSET_UNION(DST,F1,F2) \ + do { \ + (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0]; \ + (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1]; \ + } while (0) + +/* Intersection of feature sets. */ + +#define ARM_FSET_INTER(DST,F1,F2) \ + do { \ + (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0]; \ + (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1]; \ + } while (0) + +/* Exclusive disjunction. */ + +#define ARM_FSET_XOR(DST,F1,F2) \ + do { \ + (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0]; \ + (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1]; \ + } while (0) + +/* Difference of feature sets: F1 excluding the elements of F2. */ + +#define ARM_FSET_EXCLUDE(DST,F1,F2) \ + do { \ + (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0]; \ + (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1]; \ + } while (0) + +/* Test for an empty feature set. */ + +#define ARM_FSET_IS_EMPTY(A) \ + (!((A).cpu[0]) && !((A).cpu[1])) + +/* Tests whether the cpu features of A are a subset of B. */ + +#define ARM_FSET_CPU_SUBSET(A,B) \ + ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0]) \ + && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1])) + +#endif /* GCC_ARM_FLAGS_H */ diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h index a649ba59e47a00048c5ea8d5043a6495892656b5..9ae104a824b152764afbad2bf44df06657304ed7 100644 --- a/gcc/config/arm/arm-opts.h +++ b/gcc/config/arm/arm-opts.h @@ -25,6 +25,8 @@ #ifndef ARM_OPTS_H #define ARM_OPTS_H +#include "arm-flags.h" + /* The various ARM cores. */ enum processor_type { @@ -77,4 +79,24 @@ enum arm_tls_type { TLS_GNU, TLS_GNU2 }; + +struct arm_arch_core_flag +{ + const char *const name; + const arm_feature_set flags; +}; + +static const struct arm_arch_core_flag arm_arch_core_flags[] = +{ +#undef ARM_CORE +#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \ + {NAME, FLAGS}, +#include "arm-cores.def" +#undef ARM_CORE +#undef ARM_ARCH +#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \ + {NAME, FLAGS}, +#include "arm-arches.def" +#undef ARM_ARCH +}; #endif diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index fd8b6d106d13faebedf7a3539d30159c14f061c6..a20669f6f783aeefda69328d937beb8a4bbef998 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -22,6 +22,8 @@ #ifndef GCC_ARM_PROTOS_H #define GCC_ARM_PROTOS_H +#include "arm-flags.h" + extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *); extern int use_return_insn (int, rtx); extern bool use_simple_return_p (void); @@ -349,191 +351,6 @@ extern void arm_cpu_cpp_builtins (struct cpp_reader *); extern bool arm_is_constant_pool_ref (rtx); -/* Flags used to identify the presence of processor capabilities. */ - -/* Bit values used to identify processor capabilities. */ -#define FL_NONE (0) /* No flags. */ -#define FL_ANY (0xffffffff) /* All flags. */ -#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ -#define FL_ARCH3M (1 << 1) /* Extended multiply */ -#define FL_MODE26 (1 << 2) /* 26-bit mode support */ -#define FL_MODE32 (1 << 3) /* 32-bit mode support */ -#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ -#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ -#define FL_THUMB (1 << 6) /* Thumb aware */ -#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ -#define FL_STRONG (1 << 8) /* StrongARM */ -#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ -#define FL_XSCALE (1 << 10) /* XScale */ -/* spare (1 << 11) */ -#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds - media instructions. */ -#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ -#define FL_WBUF (1 << 14) /* Schedule for write buffer ops. - Note: ARM6 & 7 derivatives only. */ -#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ -#define FL_THUMB2 (1 << 16) /* Thumb-2. */ -#define FL_NOTM (1 << 17) /* Instructions not present in the 'M' - profile. */ -#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */ -#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ -#define FL_NEON (1 << 20) /* Neon instructions. */ -#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M - architecture. */ -#define FL_ARCH7 (1 << 22) /* Architecture 7. */ -#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */ -#define FL_ARCH8 (1 << 24) /* Architecture 8. */ -#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */ - -#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */ -#define FL_NO_VOLATILE_CE (1 << 27) /* No volatile memory in IT block. */ - -#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ -#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ -#define FL_ARCH6KZ (1 << 31) /* ARMv6KZ architecture. */ - -#define FL2_ARCH8_1 (1 << 0) /* Architecture 8.1. */ -#define FL2_ARCH8_2 (1 << 1) /* Architecture 8.2. */ -#define FL2_FP16INST (1 << 2) /* FP16 Instructions for ARMv8.2 and - later. */ - -/* Flags that only effect tuning, not available instructions. */ -#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ - | FL_CO_PROC) - -#define FL_FOR_ARCH2 FL_NOTM -#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) -#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) -#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) -#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) -#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) -#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) -#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) -#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) -#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE -#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) -#define FL_FOR_ARCH6J FL_FOR_ARCH6 -#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) -#define FL_FOR_ARCH6Z FL_FOR_ARCH6 -#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K -#define FL_FOR_ARCH6KZ (FL_FOR_ARCH6K | FL_ARCH6KZ) -#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) -#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) -#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) -#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) -#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV) -#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV) -#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV) -#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) -#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8) -#define FL2_FOR_ARCH8_1A FL2_ARCH8_1 -#define FL2_FOR_ARCH8_2A (FL2_FOR_ARCH8_1A | FL2_ARCH8_2) -#define FL_FOR_ARCH8M_BASE (FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV) -#define FL_FOR_ARCH8M_MAIN (FL_FOR_ARCH7M | FL_ARCH8) - -/* There are too many feature bits to fit in a single word so the set of cpu and - fpu capabilities is a structure. A feature set is created and manipulated - with the ARM_FSET macros. */ - -typedef struct -{ - unsigned long cpu[2]; -} arm_feature_set; - - -/* Initialize a feature set. */ - -#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } } - -#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE)) -#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2)) - -/* Accessors. */ - -#define ARM_FSET_CPU1(S) ((S).cpu[0]) -#define ARM_FSET_CPU2(S) ((S).cpu[1]) - -/* Useful combinations. */ - -#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE) -#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY) - -/* Tests for a specific CPU feature. */ - -#define ARM_FSET_HAS_CPU1(A, F) \ - (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F))) -#define ARM_FSET_HAS_CPU2(A, F) \ - (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F))) -#define ARM_FSET_HAS_CPU(A, F1, F2) \ - (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2))) - -/* Add a feature to a feature set. */ - -#define ARM_FSET_ADD_CPU1(DST, F) \ - do { \ - (DST).cpu[0] |= (F); \ - } while (0) - -#define ARM_FSET_ADD_CPU2(DST, F) \ - do { \ - (DST).cpu[1] |= (F); \ - } while (0) - -/* Remove a feature from a feature set. */ - -#define ARM_FSET_DEL_CPU1(DST, F) \ - do { \ - (DST).cpu[0] &= ~(F); \ - } while (0) - -#define ARM_FSET_DEL_CPU2(DST, F) \ - do { \ - (DST).cpu[1] &= ~(F); \ - } while (0) - -/* Union of feature sets. */ - -#define ARM_FSET_UNION(DST,F1,F2) \ - do { \ - (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0]; \ - (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1]; \ - } while (0) - -/* Intersection of feature sets. */ - -#define ARM_FSET_INTER(DST,F1,F2) \ - do { \ - (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0]; \ - (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1]; \ - } while (0) - -/* Exclusive disjunction. */ - -#define ARM_FSET_XOR(DST,F1,F2) \ - do { \ - (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0]; \ - (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1]; \ - } while (0) - -/* Difference of feature sets: F1 excluding the elements of F2. */ - -#define ARM_FSET_EXCLUDE(DST,F1,F2) \ - do { \ - (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0]; \ - (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1]; \ - } while (0) - -/* Test for an empty feature set. */ - -#define ARM_FSET_IS_EMPTY(A) \ - (!((A).cpu[0]) && !((A).cpu[1])) - -/* Tests whether the cpu features of A are a subset of B. */ - -#define ARM_FSET_CPU_SUBSET(A,B) \ - ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0]) \ - && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1])) - /* The bits in this mask specify which instructions we are allowed to generate. */ extern arm_feature_set insn_flags; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 35c72d30a2532797c52894f3e78c32349518afcc..1218709fa7a129bb0f3f0029b054afd4f9aa6621 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2267,13 +2267,18 @@ extern const char *arm_rewrite_mcpu (int argc, const char **argv); " :%{march=*:-march=%*}}" \ BIG_LITTLE_SPEC +extern const char *arm_target_thumb_only (int argc, const char **argv); +#define TARGET_MODE_SPEC_FUNCTIONS \ + { "target_mode_check", arm_target_thumb_only }, + /* -mcpu=native handling only makes sense with compiler running on an ARM chip. */ #if defined(__arm__) extern const char *host_detect_local_cpu (int argc, const char **argv); # define EXTRA_SPEC_FUNCTIONS \ { "local_cpu_detect", host_detect_local_cpu }, \ - BIG_LITTLE_CPU_SPEC_FUNCTIONS + BIG_LITTLE_CPU_SPEC_FUNCTIONS \ + TARGET_MODE_SPEC_FUNCTIONS # define MCPU_MTUNE_NATIVE_SPECS \ " %{march=native:%