diff mbox

[MIPS,committed] Update MIPS P5600 processor definition to avoid IMADD

Message ID 6D39441BF12EF246A7ABCE6654B023537E3F8609@hhmail02.hh.imgtec.org
State New
Headers show

Commit Message

Matthew Fortune May 4, 2016, 1:01 p.m. UTC 
The P5600 processor has a penalty for using integer multiply-add similar to
the 74k so mark it to avoid the instruction by default.

Committed as r235873.

Matthew

gcc/

	* config/mips/mips-cpus.def (p5600): Avoid IMADD by default.
	Clean up p5600 comments.

---
 gcc/ChangeLog                 | 5 +++++
 gcc/config/mips/mips-cpus.def | 8 +++-----
 2 files changed, 8 insertions(+), 5 deletions(-)

Comments

Maciej W. Rozycki May 5, 2016, 12:28 a.m. UTC | #1 
On Wed, 4 May 2016, Matthew Fortune wrote:

> diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
> index 17034f2..5df9807 100644
> --- a/gcc/config/mips/mips-cpus.def
> +++ b/gcc/config/mips/mips-cpus.def
> @@ -44,10 +44,7 @@ MIPS_CPU ("mips4", PROCESSOR_R10000, 4, 0)
>     isn't tuned to a specific processor.  */
>  MIPS_CPU ("mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY)
>  MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33, PTF_AVOID_BRANCHLIKELY)
> -/* mips32r3 is micromips hense why it uses the M4K processor.
> -   mips32r5 should use the p5600 processor, but there is no definition 
> -   for this yet, so in the short term we will use the same processor entry 
> -   as mips32r2.  */
> +/* mips32r3 is micromips hense why it uses the M4K processor.  */

 Typo here -> s/hense/hence/ -- since you've reworked the comment and 
changed the line in the course anyway, you may have well taken the 
opportunity and fixed it.

> @@ -150,7 +147,8 @@ MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, 33, 0)
>  MIPS_CPU ("interaptiv", PROCESSOR_24KF2_1, 33, 0)
>  
>  /* MIPS32 Release 5 processors.  */
> -MIPS_CPU ("p5600", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY)
> +MIPS_CPU ("p5600", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY
> +					| PTF_AVOID_IMADD)

 Not:

MIPS_CPU ("p5600", PROCESSOR_P5600, 36, (PTF_AVOID_BRANCHLIKELY
					 | PTF_AVOID_IMADD))

?

  Maciej
diff mbox

Patch

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 623b269..ea32ba5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@ 
+2016-06-04  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* config/mips/mips-cpus.def (p5600): Avoid IMADD by default.
+	Clean up p5600 comments.
+
 2016-05-04  Richard Biener  <rguenther@suse.de>
 
 	* match.pd: Add BIT_FIELD_REF canonicalizations and vector
diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
index 17034f2..5df9807 100644
--- a/gcc/config/mips/mips-cpus.def
+++ b/gcc/config/mips/mips-cpus.def
@@ -44,10 +44,7 @@  MIPS_CPU ("mips4", PROCESSOR_R10000, 4, 0)
    isn't tuned to a specific processor.  */
 MIPS_CPU ("mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY)
 MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33, PTF_AVOID_BRANCHLIKELY)
-/* mips32r3 is micromips hense why it uses the M4K processor.
-   mips32r5 should use the p5600 processor, but there is no definition 
-   for this yet, so in the short term we will use the same processor entry 
-   as mips32r2.  */
+/* mips32r3 is micromips hense why it uses the M4K processor.  */
 MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34, PTF_AVOID_BRANCHLIKELY)
 MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY)
 MIPS_CPU ("mips32r6", PROCESSOR_I6400, 37, 0)
@@ -150,7 +147,8 @@  MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, 33, 0)
 MIPS_CPU ("interaptiv", PROCESSOR_24KF2_1, 33, 0)
 
 /* MIPS32 Release 5 processors.  */
-MIPS_CPU ("p5600", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY)
+MIPS_CPU ("p5600", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY
+					| PTF_AVOID_IMADD)
 MIPS_CPU ("m5100", PROCESSOR_M5100, 36, PTF_AVOID_BRANCHLIKELY)
 MIPS_CPU ("m5101", PROCESSOR_M5100, 36, PTF_AVOID_BRANCHLIKELY)