From patchwork Mon Jun 9 14:10:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Fortune X-Patchwork-Id: 357483 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E441D14008D for ; Tue, 10 Jun 2014 00:10:17 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=KFX zoTDdcJGQH4R24XaObX6mINloO5EPtP44sqcrrBBXgpcf/imA18ARs1TuMuLJLAK EJZ9UGbzU5yH+VIcPdS6kYtlfAdl6W104CmpU8FO6ewRtnkxMhyko6uf3X+SnVXv 3EQtnwlf9xN3i/sKJyxf5rKid8QM2LeUiPkPgC5Y= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=JSkIeuU6W a5B6JDqPG9GhQYhDuw=; b=TX7/2eXWpX8VXc8Iqb82lcdmdm79Lim1UWD1nPnly sWVQ7kFkYdTvubsZMuKJ5zQPQOzbM+eViry6+N/f3Hwd7O+UnMJOdgrR+v2TpplG LneFsB3SCPY2tX9hljgy9UA5Gx11O6U+yNDj9Z1IbNtBa8mcGjB+5/ZvtNBTMwHK Uo= Received: (qmail 4891 invoked by alias); 9 Jun 2014 14:10:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 4857 invoked by uid 89); 9 Jun 2014 14:10:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Jun 2014 14:10:06 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 2332E9124EA42; Mon, 9 Jun 2014 15:09:59 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.181.6; Mon, 9 Jun 2014 15:10:02 +0100 Received: from LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9]) by LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9%17]) with mapi id 14.03.0174.001; Mon, 9 Jun 2014 15:10:01 +0100 From: Matthew Fortune To: Richard Sandiford CC: "'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)" Subject: [PATCH,MIPS] Remove unused code relating to reloading fcc Date: Mon, 9 Jun 2014 14:10:00 +0000 Message-ID: <6D39441BF12EF246A7ABCE6654B02353550259@LEMAIL01.le.imgtec.org> MIME-Version: 1.0 X-IsSubscribed: yes This is a small clean-up patch to remove code relating to reloading or moving mips fcc registers. At some point in the past these registers were allocated as part of register allocation but they are now statically allocated in the backend in a round robin fashion. The code for reloading them is therefore not necessary any more. The move costs are also irrelevant so are replaced with a comment instead (but the cases can just be deleted if that is preferred). Matthew gcc/ * config/mips/mips-protos.h (mips_expand_fcc_reload): Remove. * config/mips/mips.c (mips_expand_fcc_reload): Remove. (mips_move_to_gpr_cost): ST_REGS can't be moved. (mips_move_from_gpr_cost): Likewise. (mips_register_move_cost): Likewise. --- gcc/config/mips/mips-protos.h | 1 - gcc/config/mips/mips.c | 41 ++++------------------------------------- 2 files changed, 4 insertions(+), 38 deletions(-) bool @@ -12045,8 +12016,8 @@ mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED, return 4; case ST_REGS: - /* LUI followed by MOVF. */ - return 4; + /* Not possible. ST_REGS are never moved. */ + return 0; case COP0_REGS: case COP2_REGS: @@ -12082,9 +12053,8 @@ mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to) return 4; case ST_REGS: - /* A secondary reload through an FPR scratch. */ - return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS) - + mips_register_move_cost (mode, FP_REGS, ST_REGS)); + /* Not possible. ST_REGS are never moved. */ + return 0; case COP0_REGS: case COP2_REGS: @@ -12117,9 +12087,6 @@ mips_register_move_cost (enum machine_mode mode, if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode)) /* MOV.FMT. */ return 4; - if (to == ST_REGS) - /* The sequence generated by mips_expand_fcc_reload. */ - return 8; } /* Handle cases in which only one class deviates from the ideal. */ diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 0b8125a..0b32a70 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -232,7 +232,6 @@ extern bool mips_use_pic_fn_addr_reg_p (const_rtx); extern rtx mips_expand_call (enum mips_call_type, rtx, rtx, rtx, rtx, bool); extern void mips_split_call (rtx, rtx); extern bool mips_get_pic_call_symbol (rtx *, int); -extern void mips_expand_fcc_reload (rtx, rtx, rtx); extern void mips_set_return_address (rtx, rtx); extern bool mips_move_by_pieces_p (unsigned HOST_WIDE_INT, unsigned int); extern bool mips_store_by_pieces_p (unsigned HOST_WIDE_INT, unsigned int); diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 73b6963..1fb5ba2 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -7195,35 +7195,6 @@ mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) return true; } -/* Emit code to move general operand SRC into condition-code - register DEST given that SCRATCH is a scratch TFmode FPR. - The sequence is: - - FP1 = SRC - FP2 = 0.0f - DEST = FP2 < FP1 - - where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */ - -void -mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch) -{ - rtx fp1, fp2; - - /* Change the source to SFmode. */ - if (MEM_P (src)) - src = adjust_address (src, SFmode, 0); - else if (REG_P (src) || GET_CODE (src) == SUBREG) - src = gen_rtx_REG (SFmode, true_regnum (src)); - - fp1 = gen_rtx_REG (SFmode, REGNO (scratch)); - fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT); - - mips_emit_move (copy_rtx (fp1), src); - mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode)); - emit_insn (gen_slt_sf (dest, fp2, fp1)); -} - /* Implement MOVE_BY_PIECES_P. */