From patchwork Tue Jan 6 12:42:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Fortune X-Patchwork-Id: 425641 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7E32B140082 for ; Tue, 6 Jan 2015 23:43:06 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=pmg WKrfoSXwdpIzk0298HJX4o8KfioqPAwdMGFsU2IDNzFVB1hw7T/Ar8K8/NMBIom3 VdFmMgfawnr4WE3Jtfw+gWyo6xHGly+/eYUD9diT9ckG2idl7Frlqw09pnlaYTZX nua8mT2D5RVPuGR33DSpPT8bFsFpyAKeFKJRKj7w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=93Uwpy89T KO2JbsId2ir7le3LA8=; b=gK3bhTzXzFpCjxGnN9R7nlF1rx0kyfqnV2PTheFnA FRMdKNIdeJsWwO+C43HgblISyC5SJTPr0TlUN3OoG+815bW0omYeIlCifj816Byr nKbUXfAG7kFiCkCCr+hNHJJ2Kf073Gi2ddmDazTrJ7lFhG2GJz14ENItZdYZzQ2j ZA= Received: (qmail 19468 invoked by alias); 6 Jan 2015 12:42:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 19449 invoked by uid 89); 6 Jan 2015 12:42:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 06 Jan 2015 12:42:54 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 1E0D696358825; Tue, 6 Jan 2015 12:42:48 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 6 Jan 2015 12:42:50 +0000 Received: from LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9]) by LEMAIL01.le.imgtec.org ([fe80::5ae:ee16:f4b9:cda9%17]) with mapi id 14.03.0210.002; Tue, 6 Jan 2015 12:42:49 +0000 From: Matthew Fortune To: "Moore, Catherine (Catherine_Moore@mentor.com)" CC: "'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)" Subject: [MIPS] Update the ZC constraint for MIPSR6 and use it Date: Tue, 6 Jan 2015 12:42:49 +0000 Message-ID: <6D39441BF12EF246A7ABCE6654B0235320F9651B@LEMAIL01.le.imgtec.org> MIME-Version: 1.0 X-IsSubscribed: yes Update the ZC constraint for MIPSR6 to allow it to be used as the memory operand for implementations of atomic operations. Also switch the internal implementation of atomic operations to use ZC instead of ZR. This fix accurately describes the memory constraints for the LL and SC instructions. An offset can therefore be used to access a data item (ie. %lo ()) rather than always having to load the address into a register. Tested for mips32r2, mips32r6 and micromips. gcc/ * config/mips/constraints.md (ZC): Add support for R6 LL/SC offsets. (ZD): Update to use ISA_HAS_PREF_LL_SC_9BIT. * config/mips/mips.h (ISA_HAS_PREFETCH_9BIT): Rename to... (ISA_HAS_PREF_LL_SC_9BIT): ... this. New macro. * config/mips/sync.md (sync_compare_and_swap): Use ZC instead of ZR for the memory operand of LL/SC. (compare_and_swap_12, sync_add): Likewise. (sync__12, sync_old__12): Likewise. (sync_new__12, sync_nand_12): Likewise. (sync_old_nand_12, sync_new_nand_12): Likewise. (sync_sub, sync_old_add): Likewise. (sync_old_sub, sync_new_add): Likewise. (sync_new_sub, sync_): Likewise. (sync_old_, sync_new_"): Likewise. (sync_nand, sync_old_nand): Likewise. (sync_new_nand, sync_lock_test_and_set): Likewise. (test_and_set_12, atomic_compare_and_swap): Likewise. (atomic_exchange_llsc, atomic_fetch_add_llsc): Likewise. * doc/md.texi (ZC): Update description. OK to commit? Thanks, Matthew --- gcc/config/mips/constraints.md | 14 ++++++------ gcc/config/mips/mips.h | 4 ++-- gcc/config/mips/sync.md | 50 +++++++++++++++++++++--------------------- gcc/doc/md.texi | 8 +++---- 4 files changed, 37 insertions(+), 39 deletions(-) diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index 816880c..f5f257d 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -309,23 +309,23 @@ (define_constraint "Yx" (match_operand 0 "low_bitmask_operand")) (define_memory_constraint "ZC" - "When compiling microMIPS code, this constraint matches a memory operand - whose address is formed from a base register and a 12-bit offset. These - operands can be used for microMIPS instructions such as @code{ll} and - @code{sc}. When not compiling for microMIPS code, @code{ZC} is - equivalent to @code{R}." + "A memory operand whose address is formed by a base register and offset + that is suitable for use in instructions with the same addressing mode + as @code{ll} and @code{sc}." (and (match_code "mem") (if_then_else (match_test "TARGET_MICROMIPS") (match_test "umips_12bit_offset_address_p (XEXP (op, 0), mode)") - (match_test "mips_address_insns (XEXP (op, 0), mode, false)")))) + (if_then_else (match_test "ISA_HAS_PREF_LL_SC_9BIT") + (match_test "mips_9bit_offset_address_p (XEXP (op, 0), mode)") + (match_test "mips_address_insns (XEXP (op, 0), mode, false)"))))) (define_address_constraint "ZD" "An address suitable for a @code{prefetch} instruction, or for any other instruction with the same addressing mode as @code{prefetch}." (if_then_else (match_test "TARGET_MICROMIPS") (match_test "umips_12bit_offset_address_p (op, mode)") - (if_then_else (match_test "ISA_HAS_PREFETCH_9BIT") + (if_then_else (match_test "ISA_HAS_PREF_LL_SC_9BIT") (match_test "mips_9bit_offset_address_p (op, mode)") (match_test "mips_address_insns (op, mode, false)")))) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 9dad480..b608b17 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1089,8 +1089,8 @@ struct mips_cpu_info { || mips_isa_rev >= 1) \ && !TARGET_MIPS16) -/* ISA has data prefetch with limited 9-bit displacement. */ -#define ISA_HAS_PREFETCH_9BIT (mips_isa_rev >= 6) +/* ISA has data prefetch, LL and SC with limited 9-bit displacement. */ +#define ISA_HAS_PREF_LL_SC_9BIT (mips_isa_rev >= 6) /* ISA has data indexed prefetch instructions. This controls use of 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. diff --git a/gcc/config/mips/sync.md b/gcc/config/mips/sync.md index cf6c05b..72d2fe4 100644 --- a/gcc/config/mips/sync.md +++ b/gcc/config/mips/sync.md @@ -59,7 +59,7 @@ (define_insn "*memory_barrier" ;; Can be removed in favor of atomic_compare_and_swap below. (define_insn "sync_compare_and_swap" [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+ZR,ZR")) + (match_operand:GPR 1 "memory_operand" "+ZC,ZC")) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ") (match_operand:GPR 3 "arith_operand" "I,d")] @@ -89,7 +89,7 @@ (define_expand "sync_compare_and_swap" ;; Helper insn for mips_expand_atomic_qihi. (define_insn "compare_and_swap_12" [(set (match_operand:SI 0 "register_operand" "=&d,&d") - (match_operand:SI 1 "memory_operand" "+ZR,ZR")) + (match_operand:SI 1 "memory_operand" "+ZC,ZC")) (set (match_dup 1) (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d") (match_operand:SI 3 "register_operand" "d,d") @@ -106,7 +106,7 @@ (define_insn "compare_and_swap_12" (set_attr "sync_insn1_op2" "5")]) (define_insn "sync_add" - [(set (match_operand:GPR 0 "memory_operand" "+ZR,ZR") + [(set (match_operand:GPR 0 "memory_operand" "+ZC,ZC") (unspec_volatile:GPR [(plus:GPR (match_dup 0) (match_operand:GPR 1 "arith_operand" "I,d"))] @@ -134,7 +134,7 @@ (define_expand "sync_" ;; Helper insn for sync_ (define_insn "sync__12" - [(set (match_operand:SI 0 "memory_operand" "+ZR") + [(set (match_operand:SI 0 "memory_operand" "+ZC") (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d") @@ -174,7 +174,7 @@ (define_expand "sync_old_" ;; Helper insn for sync_old_ (define_insn "sync_old__12" [(set (match_operand:SI 0 "register_operand" "=&d") - (match_operand:SI 1 "memory_operand" "+ZR")) + (match_operand:SI 1 "memory_operand" "+ZC")) (set (match_dup 1) (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d") @@ -217,7 +217,7 @@ (define_expand "sync_new_" (define_insn "sync_new__12" [(set (match_operand:SI 0 "register_operand" "=&d") (unspec_volatile:SI - [(match_operand:SI 1 "memory_operand" "+ZR") + [(match_operand:SI 1 "memory_operand" "+ZC") (match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d") (atomic_hiqi_op:SI (match_dup 0) @@ -257,7 +257,7 @@ (define_expand "sync_nand" ;; Helper insn for sync_nand (define_insn "sync_nand_12" - [(set (match_operand:SI 0 "memory_operand" "+ZR") + [(set (match_operand:SI 0 "memory_operand" "+ZC") (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d") @@ -296,7 +296,7 @@ (define_expand "sync_old_nand" ;; Helper insn for sync_old_nand (define_insn "sync_old_nand_12" [(set (match_operand:SI 0 "register_operand" "=&d") - (match_operand:SI 1 "memory_operand" "+ZR")) + (match_operand:SI 1 "memory_operand" "+ZC")) (set (match_dup 1) (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d") @@ -337,7 +337,7 @@ (define_expand "sync_new_nand" (define_insn "sync_new_nand_12" [(set (match_operand:SI 0 "register_operand" "=&d") (unspec_volatile:SI - [(match_operand:SI 1 "memory_operand" "+ZR") + [(match_operand:SI 1 "memory_operand" "+ZC") (match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d") (match_operand:SI 4 "reg_or_0_operand" "dJ")] @@ -360,7 +360,7 @@ (define_insn "sync_new_nand_12" (set_attr "sync_insn1_op2" "4")]) (define_insn "sync_sub" - [(set (match_operand:GPR 0 "memory_operand" "+ZR") + [(set (match_operand:GPR 0 "memory_operand" "+ZC") (unspec_volatile:GPR [(minus:GPR (match_dup 0) (match_operand:GPR 1 "register_operand" "d"))] @@ -374,7 +374,7 @@ (define_insn "sync_sub" ;; Can be removed in favor of atomic_fetch_add below. (define_insn "sync_old_add" [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+ZR,ZR")) + (match_operand:GPR 1 "memory_operand" "+ZC,ZC")) (set (match_dup 1) (unspec_volatile:GPR [(plus:GPR (match_dup 1) @@ -389,7 +389,7 @@ (define_insn "sync_old_add" (define_insn "sync_old_sub" [(set (match_operand:GPR 0 "register_operand" "=&d") - (match_operand:GPR 1 "memory_operand" "+ZR")) + (match_operand:GPR 1 "memory_operand" "+ZC")) (set (match_dup 1) (unspec_volatile:GPR [(minus:GPR (match_dup 1) @@ -404,7 +404,7 @@ (define_insn "sync_old_sub" (define_insn "sync_new_add" [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (plus:GPR (match_operand:GPR 1 "memory_operand" "+ZR,ZR") + (plus:GPR (match_operand:GPR 1 "memory_operand" "+ZC,ZC") (match_operand:GPR 2 "arith_operand" "I,d"))) (set (match_dup 1) (unspec_volatile:GPR @@ -420,7 +420,7 @@ (define_insn "sync_new_add" (define_insn "sync_new_sub" [(set (match_operand:GPR 0 "register_operand" "=&d") - (minus:GPR (match_operand:GPR 1 "memory_operand" "+ZR") + (minus:GPR (match_operand:GPR 1 "memory_operand" "+ZC") (match_operand:GPR 2 "register_operand" "d"))) (set (match_dup 1) (unspec_volatile:GPR @@ -435,7 +435,7 @@ (define_insn "sync_new_sub" (set_attr "sync_insn1_op2" "2")]) (define_insn "sync_" - [(set (match_operand:GPR 0 "memory_operand" "+ZR,ZR") + [(set (match_operand:GPR 0 "memory_operand" "+ZC,ZC") (unspec_volatile:GPR [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d") (match_dup 0))] @@ -448,7 +448,7 @@ (define_insn "sync_" (define_insn "sync_old_" [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+ZR,ZR")) + (match_operand:GPR 1 "memory_operand" "+ZC,ZC")) (set (match_dup 1) (unspec_volatile:GPR [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d") @@ -463,7 +463,7 @@ (define_insn "sync_old_" (define_insn "sync_new_" [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+ZR,ZR")) + (match_operand:GPR 1 "memory_operand" "+ZC,ZC")) (set (match_dup 1) (unspec_volatile:GPR [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d") @@ -478,7 +478,7 @@ (define_insn "sync_new_" (set_attr "sync_insn1_op2" "2")]) (define_insn "sync_nand" - [(set (match_operand:GPR 0 "memory_operand" "+ZR,ZR") + [(set (match_operand:GPR 0 "memory_operand" "+ZC,ZC") (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")] UNSPEC_SYNC_OLD_OP))] "GENERATE_LL_SC" @@ -490,7 +490,7 @@ (define_insn "sync_nand" (define_insn "sync_old_nand" [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+ZR,ZR")) + (match_operand:GPR 1 "memory_operand" "+ZC,ZC")) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")] UNSPEC_SYNC_OLD_OP))] @@ -504,7 +504,7 @@ (define_insn "sync_old_nand" (define_insn "sync_new_nand" [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+ZR,ZR")) + (match_operand:GPR 1 "memory_operand" "+ZC,ZC")) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")] UNSPEC_SYNC_NEW_OP))] @@ -519,7 +519,7 @@ (define_insn "sync_new_nand" (define_insn "sync_lock_test_and_set" [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (match_operand:GPR 1 "memory_operand" "+ZR,ZR")) + (match_operand:GPR 1 "memory_operand" "+ZC,ZC")) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")] UNSPEC_SYNC_EXCHANGE))] @@ -546,7 +546,7 @@ (define_expand "sync_lock_test_and_set" (define_insn "test_and_set_12" [(set (match_operand:SI 0 "register_operand" "=&d") - (match_operand:SI 1 "memory_operand" "+ZR")) + (match_operand:SI 1 "memory_operand" "+ZC")) (set (match_dup 1) (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d") (match_operand:SI 3 "register_operand" "d") @@ -576,7 +576,7 @@ (define_insn "atomic_compare_and_swap" ;; TODO: the obscuring unspec can be relaxed for permissive memory ;; models. ;; Same applies to other atomic_* patterns. - (unspec_volatile:GPR [(match_operand:GPR 2 "memory_operand" "+ZR,ZR") + (unspec_volatile:GPR [(match_operand:GPR 2 "memory_operand" "+ZC,ZC") (match_operand:GPR 3 "reg_or_0_operand" "dJ,dJ")] UNSPEC_ATOMIC_COMPARE_AND_SWAP)) (set (match_operand:GPR 1 "register_operand" "=&d,&d") @@ -629,7 +629,7 @@ (define_expand "atomic_exchange" (define_insn "atomic_exchange_llsc" [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+ZR,ZR")] + (unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+ZC,ZC")] UNSPEC_ATOMIC_EXCHANGE)) (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")] @@ -684,7 +684,7 @@ (define_expand "atomic_fetch_add" (define_insn "atomic_fetch_add_llsc" [(set (match_operand:GPR 0 "register_operand" "=&d,&d") - (unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+ZR,ZR")] + (unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+ZC,ZC")] UNSPEC_ATOMIC_FETCH_OP)) (set (match_dup 1) (unspec_volatile:GPR diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 7f0426c..1ea39e2 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2987,11 +2987,9 @@ Floating-point zero. An address that can be used in a non-macro load or store. @item ZC -When compiling microMIPS code, this constraint matches a memory operand -whose address is formed from a base register and a 12-bit offset. These -operands can be used for microMIPS instructions such as @code{ll} and -@code{sc}. When not compiling for microMIPS code, @code{ZC} is -equivalent to @code{R}. +A memory operand whose address is formed by a base register and offset +that is suitable for use in instructions with the same addressing mode +as @code{ll} and @code{sc}. @item ZD An address suitable for a @code{prefetch} instruction, or for any other