diff mbox

[MIPS] Remove unused code relating to reloading fcc

Message ID 6D39441BF12EF246A7ABCE6654B0235320E038AE@LEMAIL01.le.imgtec.org
State New
Headers show

Commit Message

Matthew Fortune June 17, 2014, 10:58 a.m. UTC 
Richard Sandiford <rdsandiford@googlemail.com> writes:
> Matthew Fortune <Matthew.Fortune@imgtec.com> writes:
> > This is a small clean-up patch to remove code relating to reloading or
> moving
> > mips fcc registers. At some point in the past these registers were
> allocated
> > as part of register allocation but they are now statically allocated in
> the
> > backend in a round robin fashion. The code for reloading them is therefore
> not
> > necessary any more. The move costs are also irrelevant so are replaced
> with
> > a comment instead (but the cases can just be deleted if that is
> preferred).
> 
> I think removing the cases would be better.
> 
> OK with that change.  Thanks for cleaning this up.

Re-posting as I missed removing the ST_REGS handling code from
mips_secondary_reload_class.

Is this still OK? Testsuite run on mips-unknown-linux-gnu shows no change
in pass/fail.

Regards,
Matthew

gcc/

	* config/mips/mips-protos.h (mips_expand_fcc_reload): Remove.
	* config/mips/mips.c (mips_expand_fcc_reload): Remove.
	(mips_move_to_gpr_cost): Remove ST_REGS case.
	(mips_move_from_gpr_cost): Likewise.
	(mips_register_move_cost): Likewise.
	(mips_secondary_reload_class): Likewise.

 
 bool
@@ -12044,10 +12015,6 @@ mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
       /* MFC1, etc.  */
       return 4;
 
-    case ST_REGS:
-      /* LUI followed by MOVF.  */
-      return 4;
-
     case COP0_REGS:
     case COP2_REGS:
     case COP3_REGS:
@@ -12081,11 +12048,6 @@ mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
       /* MTC1, etc.  */
       return 4;
 
-    case ST_REGS:
-      /* A secondary reload through an FPR scratch.  */
-      return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
-	      + mips_register_move_cost (mode, FP_REGS, ST_REGS));
-
     case COP0_REGS:
     case COP2_REGS:
     case COP3_REGS:
@@ -12117,9 +12079,6 @@ mips_register_move_cost (enum machine_mode mode,
       if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
 	/* MOV.FMT.  */
 	return 4;
-      if (to == ST_REGS)
-	/* The sequence generated by mips_expand_fcc_reload.  */
-	return 8;
     }
 
   /* Handle cases in which only one class deviates from the ideal.  */
@@ -12184,23 +12143,6 @@ mips_secondary_reload_class (enum reg_class rclass,
   if (ACC_REG_P (regno))
     return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
 
-  /* We can only copy a value to a condition code register from a
-     floating-point register, and even then we require a scratch
-     floating-point register.  We can only copy a value out of a
-     condition-code register into a general register.  */
-  if (reg_class_subset_p (rclass, ST_REGS))
-    {
-      if (in_p)
-	return FP_REGS;
-      return GP_REG_P (regno) ? NO_REGS : GR_REGS;
-    }
-  if (ST_REG_P (regno))
-    {
-      if (!in_p)
-	return FP_REGS;
-      return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
-    }
-
   if (reg_class_subset_p (rclass, FP_REGS))
     {
       if (MEM_P (x)

Comments

Richard Sandiford June 17, 2014, 11:18 a.m. UTC | #1 
Matthew Fortune <Matthew.Fortune@imgtec.com> writes:
> Richard Sandiford <rdsandiford@googlemail.com> writes:
>> Matthew Fortune <Matthew.Fortune@imgtec.com> writes:
>> > This is a small clean-up patch to remove code relating to reloading or
>> moving
>> > mips fcc registers. At some point in the past these registers were
>> allocated
>> > as part of register allocation but they are now statically allocated in
>> the
>> > backend in a round robin fashion. The code for reloading them is therefore
>> not
>> > necessary any more. The move costs are also irrelevant so are replaced
>> with
>> > a comment instead (but the cases can just be deleted if that is
>> preferred).
>> 
>> I think removing the cases would be better.
>> 
>> OK with that change.  Thanks for cleaning this up.
>
> Re-posting as I missed removing the ST_REGS handling code from
> mips_secondary_reload_class.
>
> Is this still OK? Testsuite run on mips-unknown-linux-gnu shows no change
> in pass/fail.

Yeah, looks good, thanks.

Richard
diff mbox

Patch

diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 0b8125a..0b32a70 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -232,7 +232,6 @@  extern bool mips_use_pic_fn_addr_reg_p (const_rtx);
 extern rtx mips_expand_call (enum mips_call_type, rtx, rtx, rtx, rtx, bool);
 extern void mips_split_call (rtx, rtx);
 extern bool mips_get_pic_call_symbol (rtx *, int);
-extern void mips_expand_fcc_reload (rtx, rtx, rtx);
 extern void mips_set_return_address (rtx, rtx);
 extern bool mips_move_by_pieces_p (unsigned HOST_WIDE_INT, unsigned int);
 extern bool mips_store_by_pieces_p (unsigned HOST_WIDE_INT, unsigned int);
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 585b755..cff1d38 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -7195,35 +7195,6 @@  mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
   return true;
 }
 

-/* Emit code to move general operand SRC into condition-code
-   register DEST given that SCRATCH is a scratch TFmode FPR.
-   The sequence is:
-
-	FP1 = SRC
-	FP2 = 0.0f
-	DEST = FP2 < FP1
-
-   where FP1 and FP2 are single-precision FPRs taken from SCRATCH.  */
-
-void
-mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
-{
-  rtx fp1, fp2;
-
-  /* Change the source to SFmode.  */
-  if (MEM_P (src))
-    src = adjust_address (src, SFmode, 0);
-  else if (REG_P (src) || GET_CODE (src) == SUBREG)
-    src = gen_rtx_REG (SFmode, true_regnum (src));
-
-  fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
-  fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
-
-  mips_emit_move (copy_rtx (fp1), src);
-  mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
-  emit_insn (gen_slt_sf (dest, fp2, fp1));
-}
-

 /* Implement MOVE_BY_PIECES_P.  */