From patchwork Thu Mar 30 10:46:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 745181 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vv1XW2cJDz9ryT for ; Thu, 30 Mar 2017 21:46:50 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="hVCzHmG3"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=Xr4Z9/focivX78hhC KfBcojFwvhAEk8xbzPWXncNfpEfF9jjaTjYE9zKVGyNSl4HDuVmh7usUIJYbFJf6 jKfc8zzqx/bRELywb3+WgxaUNZ24aa5+GDmVm5kyjI5GJU03eKjJAhsVh5TSoSKS hcTsA5bDFeCSO+phWuJVh7n6rk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=UvbkYJIpMELiSxkLhHsbMC7 NRNI=; b=hVCzHmG3yT1G7DBoXKrmH42z8oBhHBNhx34nZ1av3H8W1MlbvqPzEea 26V1BTdi1HgreXFgUFeHeQDUJEudR8D7K9choNTk/1YmxOyIMKFkz/MkNshFq6HR Cqh95J0tzvptkCyQ8gZk1YTeUfaN8E07uHTkuaGz2F2IjJwXGBLk= Received: (qmail 77558 invoked by alias); 30 Mar 2017 10:46:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 77442 invoked by uid 89); 30 Mar 2017 10:46:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=media, Best X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 30 Mar 2017 10:46:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 06340B16; Thu, 30 Mar 2017 03:46:37 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 463893F59A; Thu, 30 Mar 2017 03:46:36 -0700 (PDT) Subject: Re: [PATCH, GCC/ARM, gcc-6-branch] Fix PR80082: LDRD erronously used for 64bit load on ARMv7-R To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: From: Thomas Preudhomme Message-ID: <6886ff29-49a3-3ce2-3903-129e756ea41e@foss.arm.com> Date: Thu, 30 Mar 2017 11:46:34 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: X-IsSubscribed: yes Ping? Best regards, Thomas On 27/03/17 12:15, Thomas Preudhomme wrote: > Hi, > > Currently GCC is happy to use LDRD to perform a 64bit load on ARMv7-R, > as shown by the testcase on this patch. However, LDRD is only atomic > when LPAE extensions is available, which they are not for ARMv7-R. This > commit solve the issue by introducing a new feature bit to distinguish > LPAE extensions instead of deducing it from div instruction > availability. > > ChangeLog entries are as follow: > > *** gcc/ChangeLog *** > > 2017-03-22 Thomas Preud'homme > > PR target/80082 > * config/arm/arm-protos.h (FL_LPAE): Define macro. > (FL_FOR_ARCH7VE): Add FL_LPAE. > (arm_arch_lpae): Declare extern. > * config/arm/arm.c (arm_arch_lpae): Declare. > (arm_option_override): Define arm_arch_lpae. > * config/arm/arm.h (TARGET_HAVE_LPAE): Redefine in term of > arm_arch_lpae. > > *** gcc/testsuite/ChangeLog *** > > 2017-03-22 Thomas Preud'homme > > PR target/80082 > * gcc.target/arm/atomic_loaddi_10.c: New testcase. > * gcc.target/arm/atomic_loaddi_11.c: Likewise. > > > Testing: bootstrapped for -march=armv7ve and testsuite shows no regression. > > Is this ok for gcc-6-branch? > > Best regards, > > Thomas diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 0083673b161a49e19388c72d3a413aeb481dbfa3..dea00e42551c8295f7e83a72ddb81ae8e9c8e02d 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -360,7 +360,7 @@ extern bool arm_is_constant_pool_ref (rtx); #define FL_STRONG (1 << 8) /* StrongARM */ #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ #define FL_XSCALE (1 << 10) /* XScale */ -/* spare (1 << 11) */ +#define FL_LPAE (1 << 11) /* ARMv7-A LPAE. */ #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds media instructions. */ #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ @@ -412,7 +412,7 @@ extern bool arm_is_constant_pool_ref (rtx); #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) -#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV) +#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV | FL_LPAE) #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV) #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV) #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) @@ -608,6 +608,9 @@ extern int arm_arch_thumb2; extern int arm_arch_arm_hwdiv; extern int arm_arch_thumb_hwdiv; +/* Nonzero if this chip supports the Large Physical Address Extension. */ +extern int arm_arch_lpae; + /* Nonzero if chip disallows volatile memory access in IT block. */ extern int arm_arch_no_volatile_ce; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index ad123dde991a3e4c4b9563ee6ebb84981767988f..e93ff7f7d8583b653570cbb8605df5a10bfcc6f4 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -254,8 +254,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) /* Nonzero if this chip supports LPAE. */ -#define TARGET_HAVE_LPAE \ - (arm_arch7 && ARM_FSET_HAS_CPU1 (insn_flags, FL_FOR_ARCH7VE)) +#define TARGET_HAVE_LPAE (arm_arch_lpae) /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c3c89b866355708d91dd2a3dab1e4b33f2215ff8..44bfb53a288f57fbc43a0bd146e193b768d939d2 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -859,6 +859,9 @@ int arm_arch_thumb2; int arm_arch_arm_hwdiv; int arm_arch_thumb_hwdiv; +/* Nonzero if this chip supports the Large Physical Address Extension. */ +int arm_arch_lpae; + /* Nonzero if chip disallows volatile memory access in IT block. */ int arm_arch_no_volatile_ce; @@ -3181,6 +3184,7 @@ arm_option_override (void) arm_arch_iwmmxt2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT2); arm_arch_thumb_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB_DIV); arm_arch_arm_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARM_DIV); + arm_arch_lpae = ARM_FSET_HAS_CPU1 (insn_flags, FL_LPAE); arm_arch_no_volatile_ce = ARM_FSET_HAS_CPU1 (insn_flags, FL_NO_VOLATILE_CE); arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32); diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c new file mode 100644 index 0000000000000000000000000000000000000000..ecc3d06d0c9f5966daa3ce7e2d52e09d14e0cbc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_10.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v7ve_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v7ve } */ + +#include + +atomic_llong x = 0; + +atomic_llong get_x() +{ + return atomic_load(&x); +} + +/* { dg-final { scan-assembler "ldrd" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c new file mode 100644 index 0000000000000000000000000000000000000000..85c64ae68b1b1ee68466809f7f83d07ceabec575 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v7r_ok } */ +/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-r5" } } */ +/* { dg-options "-O2 -mcpu=cortex-r5" } */ + +#include + +atomic_llong x = 0; + +atomic_llong get_x() +{ + return atomic_load(&x); +} + +/* { dg-final { scan-assembler-not "ldrd" } } */