@@ -486,13 +486,18 @@ (define_mode_iterator DIFD [DI DF DD])
; Iterator for reciprocal estimate instructions
(define_mode_iterator RECIPF [SF DF V4SF V2DF])
-; Iterator for just SF/DF
+; SFmode or DFmode.
(define_mode_iterator SFDF [SF DF])
-; Like SFDF, but a different name to match conditional move where the
-; comparison operands may be a different mode than the input operands.
+; And again, for when we need two FP modes in a pattern.
(define_mode_iterator SFDF2 [SF DF])
+; A generic s/d attribute, for sp/dp for example.
+(define_mode_attr sd [(SF "s") (DF "d")])
+
+; "s" or nothing, for fmuls/fmul for example.
+(define_mode_attr s [(SF "s") (DF "")])
+
; Iterator for 128-bit floating point that uses the IBM double-double format
(define_mode_iterator IBM128 [(IF "FLOAT128_IBM_P (IFmode)")
(TF "FLOAT128_IBM_P (TFmode)")])
@@ -513,12 +518,6 @@ (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)")
; Iterator for ISA 3.0 supported floating point types
(define_mode_iterator FP_ISA3 [SF DF])
-; SF/DF suffix for traditional floating instructions
-(define_mode_attr Ftrad [(SF "s") (DF "")])
-
-; SF/DF suffix for VSX instructions
-(define_mode_attr Fvsx [(SF "sp") (DF "dp")])
-
; SF/DF constraint for arithmetic on traditional floating point registers
(define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
@@ -531,9 +530,6 @@ (define_mode_attr Fv [(SF "ww") (DF "wa") (DI "wa")])
; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
-; s/d suffix for things like sdiv/ddiv
-(define_mode_attr Fs [(SF "s") (DF "d")])
-
; FRE/FRES support
(define_mode_attr Ffre [(SF "fres") (DF "fre")])
(define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
@@ -4638,8 +4634,8 @@ (define_insn "*add<mode>3_fpr"
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
- fadd<Ftrad> %0,%1,%2
- xsadd<Fvsx> %x0,%x1,%x2"
+ fadd<s> %0,%1,%2
+ xsadd<sd>p %x0,%x1,%x2"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>")])
@@ -4656,8 +4652,8 @@ (define_insn "*sub<mode>3_fpr"
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
- fsub<Ftrad> %0,%1,%2
- xssub<Fvsx> %x0,%x1,%x2"
+ fsub<s> %0,%1,%2
+ xssub<sd>p %x0,%x1,%x2"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>")])
@@ -4674,8 +4670,8 @@ (define_insn "*mul<mode>3_fpr"
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
- fmul<Ftrad> %0,%1,%2
- xsmul<Fvsx> %x0,%x1,%x2"
+ fmul<s> %0,%1,%2
+ xsmul<sd>p %x0,%x1,%x2"
[(set_attr "type" "dmul")
(set_attr "isa" "*,<Fisa>")])
@@ -4700,9 +4696,9 @@ (define_insn "*div<mode>3_fpr"
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
- fdiv<Ftrad> %0,%1,%2
- xsdiv<Fvsx> %x0,%x1,%x2"
- [(set_attr "type" "<Fs>div")
+ fdiv<s> %0,%1,%2
+ xsdiv<sd>p %x0,%x1,%x2"
+ [(set_attr "type" "<sd>div")
(set_attr "isa" "*,<Fisa>")])
(define_insn "*sqrt<mode>2_internal"
@@ -4710,9 +4706,9 @@ (define_insn "*sqrt<mode>2_internal"
(sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT && TARGET_PPC_GPOPT"
"@
- fsqrt<Ftrad> %0,%1
- xssqrt<Fvsx> %x0,%x1"
- [(set_attr "type" "<Fs>sqrt")
+ fsqrt<s> %0,%1
+ xssqrt<sd>p %x0,%x1"
+ [(set_attr "type" "<sd>sqrt")
(set_attr "isa" "*,<Fisa>")])
(define_expand "sqrt<mode>2"
@@ -4733,14 +4729,14 @@ (define_expand "sqrt<mode>2"
})
;; Floating point reciprocal approximation
-(define_insn "fre<Fs>"
+(define_insn "fre<sd>"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")]
UNSPEC_FRES))]
"TARGET_<FFRE>"
"@
- fre<Ftrad> %0,%1
- xsre<Fvsx> %x0,%x1"
+ fre<s> %0,%1
+ xsre<sd>p %x0,%x1"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>")])
@@ -4750,8 +4746,8 @@ (define_insn "*rsqrt<mode>2"
UNSPEC_RSQRT))]
"RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
"@
- frsqrte<Ftrad> %0,%1
- xsrsqrte<Fvsx> %x0,%x1"
+ frsqrte<s> %0,%1
+ xsrsqrte<sd>p %x0,%x1"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>")])
@@ -9390,8 +9386,8 @@ (define_insn "*mov<mode>_update1"
&& (!avoiding_indexed_address_p (<MODE>mode)
|| !gpc_reg_operand (operands[2], Pmode))"
"@
- lf<Fs>ux %3,%0,%2
- lf<Fs>u %3,%2(%0)"
+ lf<sd>ux %3,%0,%2
+ lf<sd>u %3,%2(%0)"
[(set_attr "type" "fpload")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")
@@ -9407,8 +9403,8 @@ (define_insn "*mov<mode>_update2"
&& (!avoiding_indexed_address_p (<MODE>mode)
|| !gpc_reg_operand (operands[2], Pmode))"
"@
- stf<Fs>ux %3,%0,%2
- stf<Fs>u %3,%2(%0)"
+ stf<sd>ux %3,%0,%2
+ stf<sd>u %3,%2(%0)"
[(set_attr "type" "fpstore")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")
@@ -13376,9 +13372,9 @@ (define_insn "*fma<mode>4_fpr"
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))]
"TARGET_HARD_FLOAT"
"@
- fmadd<Ftrad> %0,%1,%2,%3
- xsmadda<Fvsx> %x0,%x1,%x2
- xsmaddm<Fvsx> %x0,%x1,%x3"
+ fmadd<s> %0,%1,%2,%3
+ xsmadda<sd>p %x0,%x1,%x2
+ xsmaddm<sd>p %x0,%x1,%x3"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>,<Fisa>")])
@@ -13400,9 +13396,9 @@ (define_insn "*fms<mode>4_fpr"
(neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
"TARGET_HARD_FLOAT"
"@
- fmsub<Ftrad> %0,%1,%2,%3
- xsmsuba<Fvsx> %x0,%x1,%x2
- xsmsubm<Fvsx> %x0,%x1,%x3"
+ fmsub<s> %0,%1,%2,%3
+ xsmsuba<sd>p %x0,%x1,%x2
+ xsmsubm<sd>p %x0,%x1,%x3"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>,<Fisa>")])
@@ -13448,9 +13444,9 @@ (define_insn "*nfma<mode>4_fpr"
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
"TARGET_HARD_FLOAT"
"@
- fnmadd<Ftrad> %0,%1,%2,%3
- xsnmadda<Fvsx> %x0,%x1,%x2
- xsnmaddm<Fvsx> %x0,%x1,%x3"
+ fnmadd<s> %0,%1,%2,%3
+ xsnmadda<sd>p %x0,%x1,%x2
+ xsnmaddm<sd>p %x0,%x1,%x3"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>,<Fisa>")])
@@ -13475,9 +13471,9 @@ (define_insn "*nfmssf4_fpr"
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))))]
"TARGET_HARD_FLOAT"
"@
- fnmsub<Ftrad> %0,%1,%2,%3
- xsnmsuba<Fvsx> %x0,%x1,%x2
- xsnmsubm<Fvsx> %x0,%x1,%x3"
+ fnmsub<s> %0,%1,%2,%3
+ xsnmsuba<sd>p %x0,%x1,%x2
+ xsnmsubm<sd>p %x0,%x1,%x3"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>,<Fisa>")])
@@ -4612,7 +4612,7 @@ (define_expand "xststdcqp_<mode>"
;; (The lt bit is set if operand 1 is negative. The eq bit is set
;; if any of the conditions tested by operand 2 are satisfied.
;; The gt and unordered bits are cleared to zero.)
-(define_expand "xststdc<Fvsx>"
+(define_expand "xststdc<sd>p"
[(set (match_dup 3)
(compare:CCFP
(unspec:SFDF
@@ -4647,7 +4647,7 @@ (define_expand "xststdcnegqp_<mode>"
})
;; The VSX Scalar Test Negative Double- and Single-Precision
-(define_expand "xststdcneg<Fvsx>"
+(define_expand "xststdcneg<sd>p"
[(set (match_dup 2)
(compare:CCFP
(unspec:SFDF
@@ -4676,7 +4676,7 @@ (define_insn "*xststdcqp_<mode>"
"xststdcqp %0,%1,%2"
[(set_attr "type" "fpcompare")])
-(define_insn "*xststdc<Fvsx>"
+(define_insn "*xststdc<sd>p"
[(set (match_operand:CCFP 0 "" "=y")
(compare:CCFP
(unspec:SFDF [(match_operand:SFDF 1 "vsx_register_operand" "wa")
@@ -4684,7 +4684,7 @@ (define_insn "*xststdc<Fvsx>"
UNSPEC_VSX_STSTDC)
(match_operand:SI 3 "zero_constant" "j")))]
"TARGET_P9_VECTOR"
- "xststdc<Fvsx> %0,%x1,%2"
+ "xststdc<sd>p %0,%x1,%2"
[(set_attr "type" "fpcompare")])
;; VSX Vector Extract Exponent Double and Single Precision