From patchwork Sat Jun 11 10:24:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 1642285 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=KyPIGIHT; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LKvBk2c0Sz9sFk for ; Sat, 11 Jun 2022 20:26:36 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2DA0E38196F7 for ; Sat, 11 Jun 2022 10:26:29 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2DA0E38196F7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1654943189; bh=FF4JYZFjJZqr3SNOQmRfuHfAZsoPNxZ8+wfVRq9gyXo=; h=Date:Subject:To:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=KyPIGIHT45PZFXlZQlNaaVONb03OTcQMMIn+ZpPxQiI2jBWeNm8X8VgUub+A7ubnn ybjNfBXRdVe8HZ5COxCalWkwZ/iYiAHk4qq9CEws3ELSD0yMYKXcau0wiYr06aM0k2 NdFIa/NsFQYCZ0dhWKL6dD++u3FLaofGTwqnGqj0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from nh503-vm2.bullet.mail.kks.yahoo.co.jp (nh503-vm2.bullet.mail.kks.yahoo.co.jp [183.79.56.188]) by sourceware.org (Postfix) with SMTP id C157F3834F1F for ; Sat, 11 Jun 2022 10:26:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C157F3834F1F Received: from [183.79.100.139] by nh503.bullet.mail.kks.yahoo.co.jp with NNFMP; 11 Jun 2022 10:26:03 -0000 Received: from [183.79.100.137] by t502.bullet.mail.kks.yahoo.co.jp with NNFMP; 11 Jun 2022 10:26:03 -0000 Received: from [127.0.0.1] by omp506.mail.kks.yahoo.co.jp with NNFMP; 11 Jun 2022 10:26:03 -0000 X-Yahoo-Newman-Property: ymail-3 X-Yahoo-Newman-Id: 808760.77531.bm@omp506.mail.kks.yahoo.co.jp Received: (qmail 12703 invoked by alias); 11 Jun 2022 10:26:03 -0000 Received: from unknown (HELO ?192.168.2.3?) (175.177.45.176 with ) by smtp5009.mail.kks.ynwp.yahoo.co.jp with SMTP; 11 Jun 2022 10:26:03 -0000 X-YMail-JAS: IJ7rL9UVM1lWawAnFWt4VT8RTOnnY6v.F5UaiFMdvaqar8oeYPrHZnqOR0EN39lp7aL4cmmd6ewixPlrPkndk33mWlE4crfqmuyGayPRs3CYg4RTLiuHKHWb3cBaZsQrRFckSbr4Gg-- X-Apparently-From: X-YMail-OSG: wPrmEO8VM1ktEAAGdWtNB8WIFKFq4TghbpI_.rYzWbnPIbj SZvyd2B4j.vqfvg3ZddxJBDJa_Tqqxv2FORNdYwF0FJwrFdEl3DjZNDknK1h w_0eTTNc__oKu5Yx1fDm1.3nfT3y1u7vquD9cVRHYo_tYqL5fleWfO11Zi64 NPadpkZqLrmHYBa_xXlpfuGJXy89i._EkHVXKoDTljjA0hIAfzlRxMFOVGUd 9ZAkZRMdZ4dZt2VMkJL5iRZcifz5btY8m.KXb0GDySTW13DFRPzNwaqnQoDS Gm2QdpoOyTJ2WMs_b2fmpDPwhu.cD6mHfJt.jWO3xfWIXZ6kUe5KFnZ0DgMW Or4bLPVNDkq41L2Iq2UTVlR.1.EXTFsydLOd00l3slXOc0esC.Q9B4HGpWdC MvUzX9ih_H5pLNTMEBMH.Cwaj5Y8nhf2mHAxpZSYAV0VHFC63o1hXghC895W 3KD11ogK2X08LUvOwo1Oi1AijjZY.lDy62c3lJYqvG1keIWmPeD1FDdN7oNI rbjugvt2nReUGsFF3AXEzw.9O.1U.h6Ci.Z8SoJA.rC7AXZ62om6HtHjpagz hmkQ8dxWQnCSp0wf0EFULW3mLsMFv.n118sUDfPekLYDKaCZ2KWSBRLK7Ncl M5Q4.CVoBIusQdabzaURfx7CKPRZnDsdwrDuqryCTY9NIOmwL1oW6KD4D25n VN9Atq_wjTQ4AoZhJlOHvC6ERyMYSewXYQvCZsFKZ0CtrXCoPaQ2SPY9uFFI KmPs4FQ_KgGGfaNKT6thFmZuxkWoZX_p1elsjFaBN_10UJF3gPt.BImzTMdr wzxEQxu5I1G9ne4AXNNju5uS_VGjpzuYTz1.K_8Wf1Pnu4x9uhre0fA3bqlQ G88ZQlvWgt_6PojHuDPG7EXsFc_HG6xLq0KzM444sRro5hxXXuK5ngSpTHLa T.HxoQHC3oNI9KRpDZw-- Message-ID: <62559df3-c5a1-0d33-035b-9f72b8656857@yahoo.co.jp> Date: Sat, 11 Jun 2022 19:24:46 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: [PATCH v3 4/4] xtensa: Improve constant synthesis for both integer and floating-point Content-Language: en-US To: Max Filippov References: <200341ff-4907-c6da-07cb-86b9b4588f84@yahoo.co.jp> <0b7a3a36-cbdf-e812-4c04-533b15c9963b@yahoo.co.jp> In-Reply-To: X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Cc: GCC Patches Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" thanks for your report. On 2022/06/11 18:05, Max Filippov wrote: > It prints > (symbol_ref/f:SI ("*.LC1") [flags 0x2] ) ah, i understand it... that is Pmode (synonym of SImode) of a memory address that points to 'u.f'. thus, the correct handling is to fail the split pattern. --- gcc/config/xtensa/xtensa-protos.h | 1 + gcc/config/xtensa/xtensa.cc | 133 +++++++++++++++--- gcc/config/xtensa/xtensa.md | 50 +++++++ .../gcc.target/xtensa/constsynth_2insns.c | 44 ++++++ .../gcc.target/xtensa/constsynth_3insns.c | 24 ++++ .../gcc.target/xtensa/constsynth_double.c | 11 ++ 6 files changed, 247 insertions(+), 16 deletions(-) create mode 100644 gcc/testsuite/gcc.target/xtensa/constsynth_2insns.c create mode 100644 gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c create mode 100644 gcc/testsuite/gcc.target/xtensa/constsynth_double.c diff --git a/gcc/config/xtensa/xtensa-protos.h b/gcc/config/xtensa/xtensa-protos.h index 30e4b54394a..c2fd750cd3a 100644 --- a/gcc/config/xtensa/xtensa-protos.h +++ b/gcc/config/xtensa/xtensa-protos.h @@ -44,6 +44,7 @@ extern int xtensa_expand_block_move (rtx *); extern int xtensa_expand_block_set_unrolled_loop (rtx *); extern int xtensa_expand_block_set_small_loop (rtx *); extern void xtensa_split_operand_pair (rtx *, machine_mode); +extern int xtensa_constantsynth (rtx, HOST_WIDE_INT); extern int xtensa_emit_move_sequence (rtx *, machine_mode); extern rtx xtensa_copy_incoming_a7 (rtx); extern void xtensa_expand_nonlocal_goto (rtx *); diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index 597a36e1a97..3477e983592 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -1037,6 +1037,123 @@ xtensa_split_operand_pair (rtx operands[4], machine_mode mode) } +/* Try to emit insns to load srcval (that cannot fit into signed 12-bit) + into dst with synthesizing a such constant value from a sequence of + load-immediate / arithmetic ones, instead of a L32R instruction + (plus a constant in litpool). */ + +static void +xtensa_emit_constantsynth (rtx dst, enum rtx_code code, + HOST_WIDE_INT imm0, HOST_WIDE_INT imm1, + rtx (*gen_op)(rtx, HOST_WIDE_INT), + HOST_WIDE_INT imm2) +{ + gcc_assert (REG_P (dst)); + emit_move_insn (dst, GEN_INT (imm0)); + emit_move_insn (dst, gen_rtx_fmt_ee (code, SImode, + dst, GEN_INT (imm1))); + if (gen_op) + emit_move_insn (dst, gen_op (dst, imm2)); +} + +static int +xtensa_constantsynth_2insn (rtx dst, HOST_WIDE_INT srcval, + rtx (*gen_op)(rtx, HOST_WIDE_INT), + HOST_WIDE_INT op_imm) +{ + int shift = exact_log2 (srcval + 1); + + if (IN_RANGE (shift, 1, 31)) + { + xtensa_emit_constantsynth (dst, LSHIFTRT, -1, 32 - shift, + gen_op, op_imm); + return 1; + } + + if (IN_RANGE (srcval, (-2048 - 32768), (2047 + 32512))) + { + HOST_WIDE_INT imm0, imm1; + + if (srcval < -32768) + imm1 = -32768; + else if (srcval > 32512) + imm1 = 32512; + else + imm1 = srcval & ~255; + imm0 = srcval - imm1; + if (TARGET_DENSITY && imm1 < 32512 && IN_RANGE (imm0, 224, 255)) + imm0 -= 256, imm1 += 256; + xtensa_emit_constantsynth (dst, PLUS, imm0, imm1, gen_op, op_imm); + return 1; + } + + shift = ctz_hwi (srcval); + if (xtensa_simm12b (srcval >> shift)) + { + xtensa_emit_constantsynth (dst, ASHIFT, srcval >> shift, shift, + gen_op, op_imm); + return 1; + } + + return 0; +} + +static rtx +xtensa_constantsynth_rtx_SLLI (rtx reg, HOST_WIDE_INT imm) +{ + return gen_rtx_ASHIFT (SImode, reg, GEN_INT (imm)); +} + +static rtx +xtensa_constantsynth_rtx_ADDSUBX (rtx reg, HOST_WIDE_INT imm) +{ + return imm == 7 + ? gen_rtx_MINUS (SImode, gen_rtx_ASHIFT (SImode, reg, GEN_INT (3)), + reg) + : gen_rtx_PLUS (SImode, gen_rtx_ASHIFT (SImode, reg, + GEN_INT (floor_log2 (imm - 1))), + reg); +} + +int +xtensa_constantsynth (rtx dst, HOST_WIDE_INT srcval) +{ + /* No need for synthesizing for what fits into MOVI instruction. */ + if (xtensa_simm12b (srcval)) + return 0; + + /* 2-insns substitution. */ + if ((optimize_size || (optimize && xtensa_extra_l32r_costs >= 1)) + && xtensa_constantsynth_2insn (dst, srcval, NULL, 0)) + return 1; + + /* 3-insns substitution. */ + if (optimize > 1 && !optimize_size && xtensa_extra_l32r_costs >= 2) + { + int shift, divisor; + + /* 2-insns substitution followed by SLLI. */ + shift = ctz_hwi (srcval); + if (IN_RANGE (shift, 1, 31) && + xtensa_constantsynth_2insn (dst, srcval >> shift, + xtensa_constantsynth_rtx_SLLI, + shift)) + return 1; + + /* 2-insns substitution followed by ADDX[248] or SUBX8. */ + if (TARGET_ADDX) + for (divisor = 3; divisor <= 9; divisor += 2) + if (srcval % divisor == 0 && + xtensa_constantsynth_2insn (dst, srcval / divisor, + xtensa_constantsynth_rtx_ADDSUBX, + divisor)) + return 1; + } + + return 0; +} + + /* Emit insns to move operands[1] into operands[0]. Return 1 if we have written out everything that needs to be done to do the move. Otherwise, return 0 and the caller will emit the move @@ -1074,22 +1191,6 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode) if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16) { - /* Try to emit MOVI + SLLI sequence, that is smaller - than L32R + literal. */ - if (optimize_size && mode == SImode && CONST_INT_P (src) - && register_operand (dst, mode)) - { - HOST_WIDE_INT srcval = INTVAL (src); - int shift = ctz_hwi (srcval); - - if (xtensa_simm12b (srcval >> shift)) - { - emit_move_insn (dst, GEN_INT (srcval >> shift)); - emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift))); - return 1; - } - } - src = force_const_mem (SImode, src); operands[1] = src; } diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index f6c6be4af24..d806d43d129 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -937,6 +937,19 @@ (set_attr "mode" "SI") (set_attr "length" "2,2,2,2,2,2,3,3,3,3,6,3,3,3,3,3")]) +(define_split + [(set (match_operand:SI 0 "register_operand") + (match_operand:SI 1 "constantpool_operand"))] + "! optimize_debug && reload_completed" + [(const_int 0)] +{ + rtx x = avoid_constant_pool_reference (operands[1]); + if (! CONST_INT_P (x)) + FAIL; + if (! xtensa_constantsynth (operands[0], INTVAL (x))) + emit_move_insn (operands[0], x); +}) + ;; 16-bit Integer moves (define_expand "movhi" @@ -1139,6 +1152,43 @@ (set_attr "mode" "SF") (set_attr "length" "3")]) +(define_split + [(set (match_operand:SF 0 "register_operand") + (match_operand:SF 1 "constantpool_operand"))] + "! optimize_debug && reload_completed" + [(const_int 0)] +{ + int i = 0; + rtx x = XEXP (operands[1], 0); + long l[2]; + if (GET_CODE (x) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (x)) + x = get_pool_constant (x); + else if (GET_CODE (x) == CONST) + { + x = XEXP (x, 0); + gcc_assert (GET_CODE (x) == PLUS + && GET_CODE (XEXP (x, 0)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)) + && CONST_INT_P (XEXP (x, 1))); + i = INTVAL (XEXP (x, 1)); + gcc_assert (i == 0 || i == 4); + i /= 4; + x = get_pool_constant (XEXP (x, 0)); + } + else + gcc_unreachable (); + if (GET_MODE (x) == SFmode) + REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l[0]); + else if (GET_MODE (x) == DFmode) + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), l); + else + FAIL; + x = gen_rtx_REG (SImode, REGNO (operands[0])); + if (! xtensa_constantsynth (x, l[i])) + emit_move_insn (x, GEN_INT (l[i])); +}) + ;; 64-bit floating point moves (define_expand "movdf" diff --git a/gcc/testsuite/gcc.target/xtensa/constsynth_2insns.c b/gcc/testsuite/gcc.target/xtensa/constsynth_2insns.c new file mode 100644 index 00000000000..ec2606ed11a --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/constsynth_2insns.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-Os } */ + +int test_0(void) +{ + return 4095; +} + +int test_1(void) +{ + return 2147483647; +} + +int test_2(void) +{ + return -34816; +} + +int test_3(void) +{ + return -2049; +} + +int test_4(void) +{ + return 2048; +} + +int test_5(void) +{ + return 34559; +} + +int test_6(void) +{ + return 43680; +} + +void test_7(int *p) +{ + *p = -1432354816; +} + +/* { dg-final { scan-assembler-not "l32r" } } */ diff --git a/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c b/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c new file mode 100644 index 00000000000..f3c4a1c7c15 --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mextra-l32r-costs=3" } */ + +int test_0(void) +{ + return 134217216; +} + +int test_1(void) +{ + return -27604992; +} + +int test_2(void) +{ + return -162279; +} + +void test_3(int *p) +{ + *p = 192437; +} + +/* { dg-final { scan-assembler-not "l32r" } } */ diff --git a/gcc/testsuite/gcc.target/xtensa/constsynth_double.c b/gcc/testsuite/gcc.target/xtensa/constsynth_double.c new file mode 100644 index 00000000000..11e5d524283 --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/constsynth_double.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-Os } */ + +void test(unsigned int count, double array[]) +{ + unsigned int i; + for (i = 0; i < count; ++i) + array[i] = 1.0; +} + +/* { dg-final { scan-assembler-not "l32r" } } */