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[Aarch64] Enable descriptors for nested functions in Ada

Message ID 6039323.u0bOnZZyyN@polaris
State New
Headers show

Commit Message

Eric Botcazou Nov. 13, 2016, 10:30 p.m. UTC
Similarly to x86, PowerPC and SPARC, this enables the use of custom run-time 
descriptors in Ada, thus eliminating the need for trampolines and executable 
stack in presence of pointers to nested functions.

Tested on Aarch64/Linux, OK for the mainline?


2016-11-13  Eric Botcazou  <ebotcazou@adacore.com>

	PR ada/67205
	* config/aarch64/aarch64.c (TARGET_CUSTOM_FUNCTION_DESCRIPTORS):
	Define.

Comments

Richard Earnshaw (lists) Feb. 14, 2017, 2:48 p.m. UTC | #1
On 13/11/16 22:30, Eric Botcazou wrote:
> Similarly to x86, PowerPC and SPARC, this enables the use of custom run-time 
> descriptors in Ada, thus eliminating the need for trampolines and executable 
> stack in presence of pointers to nested functions.
> 
> Tested on Aarch64/Linux, OK for the mainline?
> 
> 
> 2016-11-13  Eric Botcazou  <ebotcazou@adacore.com>
> 
> 	PR ada/67205
> 	* config/aarch64/aarch64.c (TARGET_CUSTOM_FUNCTION_DESCRIPTORS):
> 	Define.
> 

Sorry, missed this.

OK.

R.

> 
> p.diff
> 
> 
> Index: config/aarch64/aarch64.c
> ===================================================================
> --- config/aarch64/aarch64.c	(revision 242334)
> +++ config/aarch64/aarch64.c	(working copy)
> @@ -14502,6 +14502,10 @@ aarch64_optab_supported_p (int op, machi
>  #undef TARGET_OMIT_STRUCT_RETURN_REG
>  #define TARGET_OMIT_STRUCT_RETURN_REG true
>  
> +/* The architecture reserves bits 0 and 1 so use bit 2 for descriptors.  */
> +#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
> +#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
> +
>  struct gcc_target targetm = TARGET_INITIALIZER;
>  
>  #include "gt-aarch64.h"
>
Andreas Schwab April 3, 2017, 8:42 a.m. UTC | #2
On Nov 13 2016, Eric Botcazou <ebotcazou@adacore.com> wrote:

> Index: config/aarch64/aarch64.c
> ===================================================================
> --- config/aarch64/aarch64.c	(revision 242334)
> +++ config/aarch64/aarch64.c	(working copy)
> @@ -14502,6 +14502,10 @@ aarch64_optab_supported_p (int op, machi
>  #undef TARGET_OMIT_STRUCT_RETURN_REG
>  #define TARGET_OMIT_STRUCT_RETURN_REG true
>  
> +/* The architecture reserves bits 0 and 1 so use bit 2 for descriptors.  */
> +#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
> +#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4

In which way are the bits reserved?

This does not work for ILP32, because the descriptor address starts off
at address 4 modulo 8, and adding 4 clears the bit.

Andreas.
diff mbox

Patch

Index: config/aarch64/aarch64.c
===================================================================
--- config/aarch64/aarch64.c	(revision 242334)
+++ config/aarch64/aarch64.c	(working copy)
@@ -14502,6 +14502,10 @@  aarch64_optab_supported_p (int op, machi
 #undef TARGET_OMIT_STRUCT_RETURN_REG
 #define TARGET_OMIT_STRUCT_RETURN_REG true
 
+/* The architecture reserves bits 0 and 1 so use bit 2 for descriptors.  */
+#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
+#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-aarch64.h"