From patchwork Thu Jun 27 08:57:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 1123191 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-503853-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=suse.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="bdQSH7aU"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ZDLg5c8Nz9sCJ for ; Thu, 27 Jun 2019 18:57:46 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:to:cc:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=X0SknqHXyzo3XDM7 S70KB1jd1RQqVdvR6fLF0op4jJW3WAh2GP9/ckFvQTjwR4IXefxiWeeTktjPfGod siWQ+jVSMBoQEN5CHz8wJFd5bW3JlFNJxL0XbEIQ4lBXjPNfWA1SJybEw0//ppTp TBT82rCxJrLr9sFiDfYghhG/FsU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:to:cc:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=JmL9w3p9dl0Ct05twr+Rfl ncX1M=; b=bdQSH7aU6b7JgD3yy1foyiWCJemcmbqci6RHAE3hGAfgwbxeQbKtCX i/tPHQ5EDBnZuTSbDuHLEzniY507yHq9FDrsscO391w5aCX8mS5llvO6sf+EhR+V a1w8iY2VtqD06idi6P9VhNNGdu5boLQP3wUFkXIU8EXFlda8u9h5Y= Received: (qmail 50614 invoked by alias); 27 Jun 2019 08:57:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 50439 invoked by uid 89); 27 Jun 2019 08:57:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 spammy=xv, altogether, sk:unspec_, round X-HELO: prv1-mh.provo.novell.com Received: from prv1-mh.provo.novell.com (HELO prv1-mh.provo.novell.com) (137.65.248.33) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 27 Jun 2019 08:57:36 +0000 Received: from INET-PRV1-MTA by prv1-mh.provo.novell.com with Novell_GroupWise; Thu, 27 Jun 2019 02:57:35 -0600 Message-Id: <5D1484FD020000780023B737@prv1-mh.provo.novell.com> Date: Thu, 27 Jun 2019 02:57:33 -0600 From: "Jan Beulich" To: Cc: "Kirill Yukhin" , , Subject: [PATCH] x86: fix/improve vgf2p8affine*qb insns Mime-Version: 1.0 Content-Disposition: inline - the affine transformations are not commutative (the two source operands have entirely different meaning) - there's no need for three alternatives - the nonimmediate_operand/Bm combination can better be vector_operand/m gcc/ 2019-06-27 Jan Beulich * config/i386/sse.md (vgf2p8affineinvqb_, vgf2p8affineqb_): Drop % constraint modifier. Eliminate redundant alternative. Use vector_operand plus "m" constraint. gcc/testsuite/ 2019-06-27 Jan Beulich * gcc.target/i386/gfni-5.c: New. --- On top of this (in further patches) it looks like the Bm constraint could be dropped altogether. At the very least its combination with vector_operand is pointless, because both resolve to the same vector_memory_operand. Same goes for round{,_saeonly}_nimm_predicate, which too resolves to vector_operand. --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -22072,56 +22072,53 @@ "vpopcnt\t{%1, %0|%0, %1}") (define_insn "vgf2p8affineinvqb_" - [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v") (unspec:VI1_AVX512F - [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") - (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm") - (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")] + [(match_operand:VI1_AVX512F 1 "register_operand" "0,v") + (match_operand:VI1_AVX512F 2 "vector_operand" "xm,vm") + (match_operand:QI 3 "const_0_to_255_operand" "n,n")] UNSPEC_GF2P8AFFINEINV))] "TARGET_GFNI" "@ gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3} - vgf2p8affineinvqb\t{%3, %2, %1, %0| %0, %1, %2, %3} vgf2p8affineinvqb\t{%3, %2, %1, %0| %0, %1, %2, %3}" - [(set_attr "isa" "noavx,avx,avx512f") - (set_attr "prefix_data16" "1,*,*") + [(set_attr "isa" "noavx,avx") + (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,maybe_evex,evex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")]) (define_insn "vgf2p8affineqb_" - [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v") (unspec:VI1_AVX512F - [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") - (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm") - (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")] + [(match_operand:VI1_AVX512F 1 "register_operand" "0,v") + (match_operand:VI1_AVX512F 2 "vector_operand" "xm,vm") + (match_operand:QI 3 "const_0_to_255_operand" "n,n")] UNSPEC_GF2P8AFFINE))] "TARGET_GFNI" "@ gf2p8affineqb\t{%3, %2, %0| %0, %2, %3} - vgf2p8affineqb\t{%3, %2, %1, %0| %0, %1, %2, %3} vgf2p8affineqb\t{%3, %2, %1, %0| %0, %1, %2, %3}" - [(set_attr "isa" "noavx,avx,avx512f") - (set_attr "prefix_data16" "1,*,*") + [(set_attr "isa" "noavx,avx") + (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,maybe_evex,evex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")]) (define_insn "vgf2p8mulb_" - [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v") (unspec:VI1_AVX512F - [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") - (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")] + [(match_operand:VI1_AVX512F 1 "register_operand" "%0,v") + (match_operand:VI1_AVX512F 2 "vector_operand" "xm,vm")] UNSPEC_GF2P8MUL))] "TARGET_GFNI" "@ gf2p8mulb\t{%2, %0| %0, %2} - vgf2p8mulb\t{%2, %1, %0| %0, %1, %2} vgf2p8mulb\t{%2, %1, %0| %0, %1, %2}" - [(set_attr "isa" "noavx,avx,avx512f") - (set_attr "prefix_data16" "1,*,*") + [(set_attr "isa" "noavx,avx") + (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") - (set_attr "prefix" "orig,maybe_evex,evex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "")]) (define_insn "vpshrd_" --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/gfni-5.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -mgfni" } */ + +typedef char __attribute__((vector_size(16))) v16qi_t; + +v16qi_t test16a (v16qi_t x, v16qi_t a) +{ + asm volatile ("" : "+m" (a)); + return __builtin_ia32_vgf2p8affineqb_v16qi (x, a, 0); +} + +v16qi_t test16b (v16qi_t x, v16qi_t a) +{ + asm volatile ("" : "+m" (x)); + return __builtin_ia32_vgf2p8affineqb_v16qi (x, a, 0); +} + +/* { dg-final { scan-assembler-times "gf2p8affineqb\[ \t].*\\(" 1 } } */ +/* { dg-final { scan-assembler-times "gf2p8affineqb\[ \t].*%xmm.*%xmm" 1 } } */