[AArch64] Add -mcpu/-mtune support for Arm Ares

Hi all,

This adds support for the Arm Ares CPU for AArch64.
It implements the Armv8.2-A architecture with the optional features
of statistical profiling, dot product and FP16 on by default.

Note: Ares is a codename to enable early adopters and in time
we will add the final product name once it's announced.

Bootstrapped and tested on aarch64-none-linux-gnu.

Ok for trunk?

Thanks,
Kyrill

2018-11-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/aarch64/aarch64-cores.def (ares): Define.
     * config/aarch64/aarch64-tune.md: Regenerate.
     * doc/invoke.texi (AArch64 Options): Document ares value for mtune.

On 07/11/2018 09:47, Kyrill Tkachov wrote:
> Hi all,
> 
> This adds support for the Arm Ares CPU for AArch64.
> It implements the Armv8.2-A architecture with the optional features
> of statistical profiling, dot product and FP16 on by default.
> 
> Note: Ares is a codename to enable early adopters and in time
> we will add the final product name once it's announced.
> 
> Bootstrapped and tested on aarch64-none-linux-gnu.
> 
> Ok for trunk?
> 

OK.

R.

> Thanks,
> Kyrill
> 
> 2018-11-07  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
> 
>     * config/aarch64/aarch64-cores.def (ares): Define.
>     * config/aarch64/aarch64-tune.md: Regenerate.
>     * doc/invoke.texi (AArch64 Options): Document ares value for mtune.
> 
> aarch64-ares.patch
> 
> diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
> index b1278fc263665e6ef4b175be8ab00502e7d005c4..34062a5e88683d5abe0d3ece64fa0f2a32a17cf6 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -89,6 +89,7 @@ AARCH64_CORE("thunderx2t99",  thunderx2t99,  thunderx2t99, 8_1A,  AARCH64_FL_FOR
>  AARCH64_CORE("cortex-a55",  cortexa55, cortexa53, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1)
>  AARCH64_CORE("cortex-a75",  cortexa75, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1)
>  AARCH64_CORE("cortex-a76",  cortexa76, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1)
> +AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, cortexa72, 0x41, 0xd0c, -1)
>  
>  /* ARMv8.4-A Architecture Processors.  */
>  
> diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
> index ad52d89d247329e88a01626d2f03a370e8f75d58..fade1d4430ae3614c93e0f6af53e62064a5c5ef5 100644
> --- a/gcc/config/aarch64/aarch64-tune.md
> +++ b/gcc/config/aarch64/aarch64-tune.md
> @@ -1,5 +1,5 @@
>  ;; -*- buffer-read-only: t -*-
>  ;; Generated automatically by gentune.sh from aarch64-cores.def
>  (define_attr "tune"
> -	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55"
> +	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55"
>  	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 4253af27ec50d2968bd4168b95acd069302ebb61..5f051ed1acca32a6bd0bb673691a55b72b239c96 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -15147,13 +15147,13 @@ Specify the name of the target processor for which GCC should tune the
>  performance of the code.  Permissible values for this option are:
>  @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
>  @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
> -@samp{cortex-a76}, @samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx},
> -@samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx},
> -@samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},@samp{tsv110},
> -@samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},
> -@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},
> -@samp{cortex-a73.cortex-a53}, @samp{cortex-a75.cortex-a55},
> -@samp{cortex-a76.cortex-a55}
> +@samp{cortex-a76}, @samp{ares}, @samp{exynos-m1}, @samp{falkor},
> +@samp{qdf24xx}, @samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan},
> +@samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
> +@samp{tsv110}, @samp{thunderxt83}, @samp{thunderx2t99},
> +@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
> +@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53},
> +@samp{cortex-a75.cortex-a55}, @samp{cortex-a76.cortex-a55}
>  @samp{native}.
>  
>  The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
>